Apparatus and method for quantized convergent direction-based ray sorting

ABSTRACT

Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 16/728,375,filed Dec. 27, 2019, which is hereby incorporated by reference.

TECHNICAL FIELD

This invention relates generally to the field of graphics processors.More particularly, the invention relates to an apparatus and method forquantized convergent direction-based ray sorting.

BACKGROUND ART

Ray tracing is a technique in which a light transport is simulatedthrough physically-based rendering. Widely used in cinematic rendering,it was considered too resource-intensive for real-time performance untiljust a few years ago. One of the key operations in ray tracing isprocessing a visibility query for ray-scene intersections known as “raytraversal” which computes ray-scene intersections by traversing andintersecting nodes in a bounding volume hierarchy (BVH).

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained from thefollowing detailed description in conjunction with the followingdrawings, in which:

FIG. 1 is a block diagram of an embodiment of a computer system with aprocessor having one or more processor cores and graphics processors;

FIGS. 2A-D are a block diagrams of one embodiment of a processor havingone or more processor cores, an integrated memory controller, and anintegrated graphics processor;

FIGS. 3A-C are a block diagrams of one embodiment of a graphicsprocessor which may be a discreet graphics processing unit, or may begraphics processor integrated with a plurality of processing cores;

FIG. 4 is a block diagram of an embodiment of a graphics-processingengine for a graphics processor;

FIGS. 5A-B are a block diagrams of another embodiment of a graphicsprocessor;

FIG. 6 illustrates examples of execution circuitry and logic;

FIG. 7 illustrates a graphics processor execution unit instructionformat according to an embodiment;

FIG. 8 is a block diagram of another embodiment of a graphics processorwhich includes a graphics pipeline, a media pipeline, a display engine,thread execution logic, and a render output pipeline;

FIG. 9A is a block diagram illustrating a graphics processor commandformat according to an embodiment;

FIG. 9B is a block diagram illustrating a graphics processor commandsequence according to an embodiment;

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system according to an embodiment;

FIGS. 11A-D illustrates an exemplary IP core development system that maybe used to manufacture an integrated circuit and an exemplary packageassembly;

FIG. 12 illustrates an exemplary system on a chip integrated circuitthat may be fabricated using one or more IP cores, according to anembodiment;

FIG. 13 illustrates an exemplary graphics processor of a system on achip integrated circuit that may be fabricated using one or more IPcores;

FIG. 14 illustrate exemplary graphics processor architectures;

FIG. 15 illustrates an example of a processing architecture whichincludes ray tracing cores and tensor cores;

FIG. 16 illustrates a ray tracing cluster of nodes;

FIG. 17 illustrates additional details for example ray tracing nodes;

FIG. 18 illustrates ray compression/decompression employed in oneembodiment;

FIG. 19 illustrates one embodiment of a hybrid ray tracing architecture;

FIG. 20 illustrates example call stack references;

FIG. 21 illustrates an example set of shader record pointers;

FIG. 22 illustrates an example of a bounding volume hierarchy;

FIG. 23 illustrates one embodiment of a call stack and associatedtraversal state;

FIG. 24 illustrates one embodiment of the invention for sorting rays;

FIG. 25 illustrates an example set of rays intersecting a volume;

FIG. 26 illustrates a sort key in accordance with one embodiment of theinvention; and

FIG. 27 illustrates a method in accordance with one embodiment of theinvention.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the embodiments of the invention described below. Itwill be apparent, however, to one skilled in the art that theembodiments of the invention may be practiced without some of thesespecific details. In other instances, well-known structures and devicesare shown in block diagram form to avoid obscuring the underlyingprinciples of the embodiments of the invention.

Exemplary Graphics Processor Architectures And Data Types

System Overview

FIG. 1 is a block diagram of a processing system 100, according to anembodiment. System 100 may be used in a single processor desktop system,a multiprocessor workstation system, or a server system having a largenumber of processors 102 or processor cores 107. In one embodiment, thesystem 100 is a processing platform incorporated within asystem-on-a-chip (SoC) integrated circuit for use in mobile, handheld,or embedded devices such as within Internet-of-things (IoT) devices withwired or wireless connectivity to a local or wide area network.

In one embodiment, system 100 can include, couple with, or be integratedwithin: a server-based gaming platform; a game console, including a gameand media console; a mobile gaming console, a handheld game console, oran online game console. In some embodiments the system 100 is part of amobile phone, smart phone, tablet computing device or mobileInternet-connected device such as a laptop with low internal storagecapacity. Processing system 100 can also include, couple with, or beintegrated within: a wearable device, such as a smart watch wearabledevice; smart eyewear or clothing enhanced with augmented reality (AR)or virtual reality (VR) features to provide visual, audio or tactileoutputs to supplement real world visual, audio or tactile experiences orotherwise provide text, audio, graphics, video, holographic images orvideo, or tactile feedback; other augmented reality (AR) device; orother virtual reality (VR) device. In some embodiments, the processingsystem 100 includes or is part of a television or set top box device. Inone embodiment, system 100 can include, couple with, or be integratedwithin a self-driving vehicle such as a bus, tractor trailer, car, motoror electric power cycle, plane or glider (or any combination thereof).The self-driving vehicle may use system 100 to process the environmentsensed around the vehicle.

In some embodiments, the one or more processors 102 each include one ormore processor cores 107 to process instructions which, when executed,perform operations for system or user software. In some embodiments, atleast one of the one or more processor cores 107 is configured toprocess a specific instruction set 109. In some embodiments, instructionset 109 may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). One or more processor cores 107 may process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such as a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 can be additionallyincluded in processor 102 and may include different types of registersfor storing different types of data (e.g., integer registers, floatingpoint registers, status registers, and an instruction pointer register).Some registers may be general-purpose registers, while other registersmay be specific to the design of the processor 102.

In some embodiments, one or more processor(s) 102 are coupled with oneor more interface bus(es) 110 to transmit communication signals such asaddress, data, or control signals between processor 102 and othercomponents in the system 100. The interface bus 110, in one embodiment,can be a processor bus, such as a version of the Direct Media Interface(DMI) bus. However, processor busses are not limited to the DMI bus, andmay include one or more Peripheral Component Interconnect buses (e.g.,PCI, PCI express), memory busses, or other types of interface busses. Inone embodiment the processor(s) 102 include an integrated memorycontroller 116 and a platform controller hub 130. The memory controller116 facilitates communication between a memory device and othercomponents of the system 100, while the platform controller hub (PCH)130 provides connections to I/O devices via a local I/O bus.

The memory device 120 can be a dynamic random-access memory (DRAM)device, a static random-access memory (SRAM) device, flash memorydevice, phase-change memory device, or some other memory device havingsuitable performance to serve as process memory. In one embodiment thememory device 120 can operate as system memory for the system 100, tostore data 122 and instructions 121 for use when the one or moreprocessors 102 executes an application or process. Memory controller 116also couples with an optional external graphics processor 118, which maycommunicate with the one or more graphics processors 108 in processors102 to perform graphics and media operations. In some embodiments,graphics, media, and or compute operations may be assisted by anaccelerator 112 which is a coprocessor that can be configured to performa specialized set of graphics, media, or compute operations. Forexample, in one embodiment the accelerator 112 is a matrixmultiplication accelerator used to optimize machine learning or computeoperations. In one embodiment the accelerator 112 is a ray-tracingaccelerator that can be used to perform ray-tracing operations inconcert with the graphics processor 108. In one embodiment, an externalaccelerator 119 may be used in place of or in concert with theaccelerator 112.

In some embodiments a display device 111 can connect to the processor(s)102. The display device 111 can be one or more of an internal displaydevice, as in a mobile electronic device or a laptop device or anexternal display device attached via a display interface (e.g.,DisplayPort, etc.). In one embodiment the display device 111 can be ahead mounted display (HMD) such as a stereoscopic display device for usein virtual reality (VR) applications or augmented reality (AR)applications.

In some embodiments the platform controller hub 130 enables peripheralsto connect to memory device 120 and processor 102 via a high-speed I/Obus. The I/O peripherals include, but are not limited to, an audiocontroller 146, a network controller 134, a firmware interface 128, awireless transceiver 126, touch sensors 125, a data storage device 124(e.g., non-volatile memory, volatile memory, hard disk drive, flashmemory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 canconnect via a storage interface (e.g., SATA) or via a peripheral bus,such as a Peripheral Component Interconnect bus (e.g., PCI, PCIexpress). The touch sensors 125 can include touch screen sensors,pressure sensors, or fingerprint sensors. The wireless transceiver 126can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile networktransceiver such as a 3G, 4G, 5G, or Long-Term Evolution (LTE)transceiver. The firmware interface 128 enables communication withsystem firmware, and can be, for example, a unified extensible firmwareinterface (UEFI). The network controller 134 can enable a networkconnection to a wired network. In some embodiments, a high-performancenetwork controller (not shown) couples with the interface bus 110. Theaudio controller 146, in one embodiment, is a multi-channel highdefinition audio controller. In one embodiment the system 100 includesan optional legacy I/O controller 140 for coupling legacy (e.g.,Personal System 2 (PS/2)) devices to the system. The platform controllerhub 130 can also connect to one or more Universal Serial Bus (USB)controllers 142 connect input devices, such as keyboard and mouse 143combinations, a camera 144, or other USB input devices.

It will be appreciated that the system 100 shown is exemplary and notlimiting, as other types of data processing systems that are differentlyconfigured may also be used. For example, an instance of the memorycontroller 116 and platform controller hub 130 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 118. In one embodiment the platform controller hub 130 and/ormemory controller 116 may be external to the one or more processor(s)102. For example, the system 100 can include an external memorycontroller 116 and platform controller hub 130, which may be configuredas a memory controller hub and peripheral controller hub within a systemchipset that is in communication with the processor(s) 102.

For example, circuit boards (“sleds”) can be used on which componentssuch as CPUs, memory, and other components are placed are designed forincreased thermal performance In some examples, processing componentssuch as the processors are located on a top side of a sled while nearmemory, such as DIMMs, are located on a bottom side of the sled. As aresult of the enhanced airflow provided by this design, the componentsmay operate at higher frequencies and power levels than in typicalsystems, thereby increasing performance. Furthermore, the sleds areconfigured to blindly mate with power and data communication cables in arack, thereby enhancing their ability to be quickly removed, upgraded,reinstalled, and/or replaced. Similarly, individual components locatedon the sleds, such as processors, accelerators, memory, and data storagedrives, are configured to be easily upgraded due to their increasedspacing from each other. In the illustrative embodiment, the componentsadditionally include hardware attestation features to prove theirauthenticity.

A data center can utilize a single network architecture (“fabric”) thatsupports multiple other network architectures including Ethernet andOmni-Path. The sleds can be coupled to switches via optical fibers,which provide higher bandwidth and lower latency than typical twistedpair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due tothe high bandwidth, low latency interconnections and networkarchitecture, the data center may, in use, pool resources, such asmemory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs,neural network and/or artificial intelligence accelerators, etc.), anddata storage drives that are physically disaggregated, and provide themto compute resources (e.g., processors) on an as needed basis, enablingthe compute resources to access the pooled resources as if they werelocal.

A power supply or source can provide voltage and/or current to system100 or any component or system described herein. In one example, thepower supply includes an AC to DC (alternating current to directcurrent) adapter to plug into a wall outlet. Such AC power can berenewable energy (e.g., solar power) power source. In one example, powersource includes a DC power source, such as an external AC to DCconverter. In one example, power source or power supply includeswireless charging hardware to charge via proximity to a charging field.In one example, power source can include an internal battery,alternating current supply, motion-based power supply, solar powersupply, or fuel cell source.

FIGS. 2A-2D illustrate computing systems and graphics processorsprovided by embodiments described herein. The elements of FIGS. 2A-2Dhaving the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such.

FIG. 2A is a block diagram of an embodiment of a processor 200 havingone or more processor cores 202A-202N, an integrated memory controller214, and an integrated graphics processor 208. Processor 200 can includeadditional cores up to and including additional core 202N represented bythe dashed lined boxes. Each of processor cores 202A-202N includes oneor more internal cache units 204A-204N. In some embodiments eachprocessor core also has access to one or more shared cached units 206.The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more PCI or PCI express busses. System agent core 210 providesmanagement functionality for the various processor components. In someembodiments, system agent core 210 includes one or more integratedmemory controllers 214 to manage access to various external memorydevices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, the systemagent core 210 also includes a display controller 211 to drive graphicsprocessor output to one or more coupled displays. In some embodiments,display controller 211 may also be a separate module coupled with thegraphics processor via at least one interconnect, or may be integratedwithin the graphics processor 208.

In some embodiments, a ring-based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect 212 via an I/O link213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202A-202N and graphicsprocessor 208 can use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-202Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment, processor cores 202A-202N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. In one embodiment,processor cores 202A-202N are heterogeneous in terms of computationalcapability. Additionally, processor 200 can be implemented on one ormore chips or as an SoC integrated circuit having the illustratedcomponents, in addition to other components.

FIG. 2B is a block diagram of hardware logic of a graphics processorcore 219, according to some embodiments described herein. Elements ofFIG. 2B having the same reference numbers (or names) as the elements ofany other figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Thegraphics processor core 219, sometimes referred to as a core slice, canbe one or multiple graphics cores within a modular graphics processor.The graphics processor core 219 is exemplary of one graphics core slice,and a graphics processor as described herein may include multiplegraphics core slices based on target power and performance envelopes.Each graphics processor core 219 can include a fixed function block 230coupled with multiple sub-cores 221A-221F, also referred to assub-slices, that include modular blocks of general-purpose and fixedfunction logic.

In some embodiments, the fixed function block 230 includes ageometry/fixed function pipeline 231 that can be shared by all sub-coresin the graphics processor core 219, for example, in lower performanceand/or lower power graphics processor implementations. In variousembodiments, the geometry/fixed function pipeline 231 includes a 3Dfixed function pipeline (e.g., 3D pipeline 312 as in FIG. 3 and FIG. 4,described below) a video front-end unit, a thread spawner and threaddispatcher, and a unified return buffer manager, which manages unifiedreturn buffers (e.g., unified return buffer 418 in FIG. 4, as describedbelow).

In one embodiment the fixed function block 230 also includes a graphicsSoC interface 232, a graphics microcontroller 233, and a media pipeline234. The graphics SoC interface 232 provides an interface between thegraphics processor core 219 and other processor cores within a system ona chip integrated circuit. The graphics microcontroller 233 is aprogrammable sub-processor that is configurable to manage variousfunctions of the graphics processor core 219, including thread dispatch,scheduling, and pre-emption. The media pipeline 234 (e.g., mediapipeline 316 of FIG. 3 and FIG. 4) includes logic to facilitate thedecoding, encoding, pre-processing, and/or post-processing of multimediadata, including image and video data. The media pipeline 234 implementmedia operations via requests to compute or sampling logic within thesub-cores 221-221F.

In one embodiment the SoC interface 232 enables the graphics processorcore 219 to communicate with general-purpose application processor cores(e.g., CPUs) and/or other components within an SoC, including memoryhierarchy elements such as a shared last level cache memory, the systemRAM, and/or embedded on-chip or on-package DRAM. The SoC interface 232can also enable communication with fixed function devices within theSoC, such as camera imaging pipelines, and enables the use of and/orimplements global memory atomics that may be shared between the graphicsprocessor core 219 and CPUs within the SoC. The SoC interface 232 canalso implement power management controls for the graphics processor core219 and enable an interface between a clock domain of the graphic core219 and other clock domains within the SoC. In one embodiment the SoCinterface 232 enables receipt of command buffers from a command streamerand global thread dispatcher that are configured to provide commands andinstructions to each of one or more graphics cores within a graphicsprocessor. The commands and instructions can be dispatched to the mediapipeline 234, when media operations are to be performed, or a geometryand fixed function pipeline (e.g., geometry and fixed function pipeline231, geometry and fixed function pipeline 237) when graphics processingoperations are to be performed.

The graphics microcontroller 233 can be configured to perform variousscheduling and management tasks for the graphics processor core 219. Inone embodiment the graphics microcontroller 233 can perform graphicsand/or compute workload scheduling on the various graphics parallelengines within execution unit (EU) arrays 222A-222F, 224A-224F withinthe sub-cores 221A-221F. In this scheduling model, host softwareexecuting on a CPU core of an SoC including the graphics processor core219 can submit workloads one of multiple graphic processor doorbells,which invokes a scheduling operation on the appropriate graphics engine.Scheduling operations include determining which workload to run next,submitting a workload to a command streamer, pre-empting existingworkloads running on an engine, monitoring progress of a workload, andnotifying host software when a workload is complete. In one embodimentthe graphics microcontroller 233 can also facilitate low-power or idlestates for the graphics processor core 219, providing the graphicsprocessor core 219 with the ability to save and restore registers withinthe graphics processor core 219 across low-power state transitionsindependently from the operating system and/or graphics driver softwareon the system.

The graphics processor core 219 may have greater than or fewer than theillustrated sub-cores 221A-221F, up to N modular sub-cores. For each setof N sub-cores, the graphics processor core 219 can also include sharedfunction logic 235, shared and/or cache memory 236, a geometry/fixedfunction pipeline 237, as well as additional fixed function logic 238 toaccelerate various graphics and compute processing operations. Theshared function logic 235 can include logic units associated with theshared function logic 420 of FIG. 4 (e.g., sampler, math, and/orinter-thread communication logic) that can be shared by each N sub-coreswithin the graphics processor core 219. The shared and/or cache memory236 can be a last-level cache for the set of N sub-cores 221A-221Fwithin the graphics processor core 219, and can also serve as sharedmemory that is accessible by multiple sub-cores. The geometry/fixedfunction pipeline 237 can be included instead of the geometry/fixedfunction pipeline 231 within the fixed function block 230 and caninclude the same or similar logic units.

In one embodiment the graphics processor core 219 includes additionalfixed function logic 238 that can include various fixed functionacceleration logic for use by the graphics processor core 219. In oneembodiment the additional fixed function logic 238 includes anadditional geometry pipeline for use in position only shading. Inposition-only shading, two geometry pipelines exist, the full geometrypipeline within the geometry/fixed function pipeline 238, 231, and acull pipeline, which is an additional geometry pipeline which may beincluded within the additional fixed function logic 238. In oneembodiment the cull pipeline is a trimmed down version of the fullgeometry pipeline. The full pipeline and the cull pipeline can executedifferent instances of the same application, each instance having aseparate context. Position only shading can hide long cull runs ofdiscarded triangles, enabling shading to be completed earlier in someinstances. For example and in one embodiment the cull pipeline logicwithin the additional fixed function logic 238 can execute positionshaders in parallel with the main application and generally generatescritical results faster than the full pipeline, as the cull pipelinefetches and shades only the position attribute of the vertices, withoutperforming rasterization and rendering of the pixels to the framebuffer. The cull pipeline can use the generated critical results tocompute visibility information for all the triangles without regard towhether those triangles are culled. The full pipeline (which in thisinstance may be referred to as a replay pipeline) can consume thevisibility information to skip the culled triangles to shade only thevisible triangles that are finally passed to the rasterization phase.

In one embodiment the additional fixed function logic 238 can alsoinclude machine-learning acceleration logic, such as fixed functionmatrix multiplication logic, for implementations including optimizationsfor machine learning training or inferencing.

Within each graphics sub-core 221A-221F includes a set of executionresources that may be used to perform graphics, media, and computeoperations in response to requests by graphics pipeline, media pipeline,or shader programs. The graphics sub-cores 221A-221F include multiple EUarrays 222A-222F, 224A-224F, thread dispatch and inter-threadcommunication (TD/IC) logic 223A-223F, a 3D (e.g., texture) sampler225A-225F, a media sampler 206A-206F, a shader processor 227A-227F, andshared local memory (SLM) 228A-228F. The EU arrays 222A-222F, 224A-224Feach include multiple execution units, which are general-purposegraphics processing units capable of performing floating-point andinteger/fixed-point logic operations in service of a graphics, media, orcompute operation, including graphics, media, or compute shaderprograms. The TD/IC logic 223A-223F performs local thread dispatch andthread control operations for the execution units within a sub-core andfacilitate communication between threads executing on the executionunits of the sub-core. The 3D sampler 225A-225F can read texture orother 3D graphics related data into memory. The 3D sampler can readtexture data differently based on a configured sample state and thetexture format associated with a given texture. The media sampler206A-206F can perform similar read operations based on the type andformat associated with media data. In one embodiment, each graphicssub-core 221A-221F can alternately include a unified 3D and mediasampler. Threads executing on the execution units within each of thesub-cores 221A-221F can make use of shared local memory 228A-228F withineach sub-core, to enable threads executing within a thread group toexecute using a common pool of on-chip memory.

FIG. 2C illustrates a graphics processing unit (GPU) 239 that includesdedicated sets of graphics processing resources arranged into multi-coregroups 240A-240N. While the details of only a single multi-core group240A are provided, it will be appreciated that the other multi-coregroups 240B-240N may be equipped with the same or similar sets ofgraphics processing resources.

As illustrated, a multi-core group 240A may include a set of graphicscores 243, a set of tensor cores 244, and a set of ray tracing cores245. A scheduler/dispatcher 241 schedules and dispatches the graphicsthreads for execution on the various cores 243, 244, 245. A set ofregister files 242 store operand values used by the cores 243, 244, 245when executing the graphics threads. These may include, for example,integer registers for storing integer values, floating point registersfor storing floating point values, vector registers for storing packeddata elements (integer and/or floating point data elements) and tileregisters for storing tensor/matrix values. In one embodiment, the tileregisters are implemented as combined sets of vector registers.

One or more combined level 1 (L1) caches and shared memory units 247store graphics data such as texture data, vertex data, pixel data, raydata, bounding volume data, etc., locally within each multi-core group240A. One or more texture units 247 can also be used to performtexturing operations, such as texture mapping and sampling. A Level 2(L2) cache 253 shared by all or a subset of the multi-core groups240A-240N stores graphics data and/or instructions for multipleconcurrent graphics threads. As illustrated, the L2 cache 253 may beshared across a plurality of multi-core groups 240A-240N. One or morememory controllers 248 couple the GPU 239 to a memory 249 which may be asystem memory (e.g., DRAM) and/or a dedicated graphics memory (e.g.,GDDR6 memory).

Input/output (I/O) circuitry 250 couples the GPU 239 to one or more I/Odevices 252 such as digital signal processors (DSPs), networkcontrollers, or user input devices. An on-chip interconnect may be usedto couple the I/O devices 252 to the GPU 239 and memory 249. One or moreI/O memory management units (IOMMUs) 251 of the I/O circuitry 250 couplethe I/O devices 252 directly to the system memory 249. In oneembodiment, the IOMMU 251 manages multiple sets of page tables to mapvirtual addresses to physical addresses in system memory 249. In thisembodiment, the I/O devices 252, CPU(s) 246, and GPU(s) 239 may sharethe same virtual address space.

In one implementation, the IOMMU 251 supports virtualization. In thiscase, it may manage a first set of page tables to map guest/graphicsvirtual addresses to guest/graphics physical addresses and a second setof page tables to map the guest/graphics physical addresses tosystem/host physical addresses (e.g., within system memory 249). Thebase addresses of each of the first and second sets of page tables maybe stored in control registers and swapped out on a context switch(e.g., so that the new context is provided with access to the relevantset of page tables). While not illustrated in FIG. 2C, each of the cores243, 244, 245 and/or multi-core groups 240A-240N may include translationlookaside buffers (TLBs) to cache guest virtual to guest physicaltranslations, guest physical to host physical translations, and guestvirtual to host physical translations.

In one embodiment, the CPUs 246, GPUs 239, and I/O devices 252 areintegrated on a single semiconductor chip and/or chip package. Theillustrated memory 249 may be integrated on the same chip or may becoupled to the memory controllers 248 via an off-chip interface. In oneimplementation, the memory 249 comprises GDDR6 memory which shares thesame virtual address space as other physical system-level memories,although the underlying principles of the invention are not limited tothis specific implementation.

In one embodiment, the tensor cores 244 include a plurality of executionunits specifically designed to perform matrix operations, which are thefundamental compute operation used to perform deep learning operations.For example, simultaneous matrix multiplication operations may be usedfor neural network training and inferencing. The tensor cores 244 mayperform matrix processing using a variety of operand precisionsincluding single precision floating-point (e.g., 32 bits),half-precision floating point (e.g., 16 bits), integer words (16 bits),bytes (8 bits), and half-bytes (4 bits). In one embodiment, a neuralnetwork implementation extracts features of each rendered scene,potentially combining details from multiple frames, to construct ahigh-quality final image.

In deep learning implementations, parallel matrix multiplication workmay be scheduled for execution on the tensor cores 244. The training ofneural networks, in particular, requires a significant number matrix dotproduct operations. In order to process an inner-product formulation ofan N×N×N matrix multiply, the tensor cores 244 may include at least Ndot-product processing elements. Before the matrix multiply begins, oneentire matrix is loaded into tile registers and at least one column of asecond matrix is loaded each cycle for N cycles. Each cycle, there are Ndot products that are processed.

Matrix elements may be stored at different precisions depending on theparticular implementation, including 16-bit words, 8-bit bytes (e.g.,INT8) and 4-bit half-bytes (e.g., INT4). Different precision modes maybe specified for the tensor cores 244 to ensure that the most efficientprecision is used for different workloads (e.g., such as inferencingworkloads which can tolerate quantization to bytes and half-bytes).

In one embodiment, the ray tracing cores 245 accelerate ray tracingoperations for both real-time ray tracing and non-real-time ray tracingimplementations. In particular, the ray tracing cores 245 include raytraversal/intersection circuitry for performing ray traversal usingbounding volume hierarchies (BVHs) and identifying intersections betweenrays and primitives enclosed within the BVH volumes. The ray tracingcores 245 may also include circuitry for performing depth testing andculling (e.g., using a Z buffer or similar arrangement). In oneimplementation, the ray tracing cores 245 perform traversal andintersection operations in concert with the image denoising techniquesdescribed herein, at least a portion of which may be executed on thetensor cores 244. For example, in one embodiment, the tensor cores 244implement a deep learning neural network to perform denoising of framesgenerated by the ray tracing cores 245. However, the CPU(s) 246,graphics cores 243, and/or ray tracing cores 245 may also implement allor a portion of the denoising and/or deep learning algorithms.

In addition, as described above, a distributed approach to denoising maybe employed in which the GPU 239 is in a computing device coupled toother computing devices over a network or high speed interconnect. Inthis embodiment, the interconnected computing devices share neuralnetwork learning/training data to improve the speed with which theoverall system learns to perform denoising for different types of imageframes and/or different graphics applications.

In one embodiment, the ray tracing cores 245 process all BVH traversaland ray-primitive intersections, saving the graphics cores 243 frombeing overloaded with thousands of instructions per ray. In oneembodiment, each ray tracing core 245 includes a first set ofspecialized circuitry for performing bounding box tests (e.g., fortraversal operations) and a second set of specialized circuitry forperforming the ray-triangle intersection tests (e.g., intersecting rayswhich have been traversed). Thus, in one embodiment, the multi-coregroup 240A can simply launch a ray probe, and the ray tracing cores 245independently perform ray traversal and intersection and return hit data(e.g., a hit, no hit, multiple hits, etc.) to the thread context. Theother cores 243, 244 are freed to perform other graphics or compute workwhile the ray tracing cores 245 perform the traversal and intersectionoperations.

In one embodiment, each ray tracing core 245 includes a traversal unitto perform BVH testing operations and an intersection unit whichperforms ray-primitive intersection tests. The intersection unitgenerates a “hit”, “no hit”, or “multiple hit” response, which itprovides to the appropriate thread. During the traversal andintersection operations, the execution resources of the other cores(e.g., graphics cores 243 and tensor cores 244) are freed to performother forms of graphics work.

In one particular embodiment described below, a hybrid rasterization/raytracing approach is used in which work is distributed between thegraphics cores 243 and ray tracing cores 245.

In one embodiment, the ray tracing cores 245 (and/or other cores 243,244) include hardware support for a ray tracing instruction set such asMicrosoft's DirectX Ray Tracing (DXR) which includes a DispatchRayscommand, as well as ray-generation, closest-hit, any-hit, and missshaders, which enable the assignment of unique sets of shaders andtextures for each object. Another ray tracing platform which may besupported by the ray tracing cores 245, graphics cores 243 and tensorcores 244 is Vulkan 1.1.85. Note, however, that the underlyingprinciples of the invention are not limited to any particular raytracing ISA.

In general, the various cores 245, 244, 243 may support a ray tracinginstruction set that includes instructions/functions for ray generation,closest hit, any hit, ray-primitive intersection, per-primitive andhierarchical bounding box construction, miss, visit, and exceptions.More specifically, one embodiment includes ray tracing instructions toperform the following functions:

Ray Generation—Ray generation instructions may be executed for eachpixel, sample, or other user-defined work assignment.

Closest Hit—A closest hit instruction may be executed to locate theclosest intersection point of a ray with primitives within a scene.

Any Hit—An any hit instruction identifies multiple intersections betweena ray and primitives within a scene, potentially to identify a newclosest intersection point.

Intersection—An intersection instruction performs a ray-primitiveintersection test and outputs a result.

Per-primitive Bounding box Construction—This instruction builds abounding box around a given primitive or group of primitives (e.g., whenbuilding a new BVH or other acceleration data structure).

Miss—Indicates that a ray misses all geometry within a scene, orspecified region of a scene.

Visit—Indicates the children volumes a ray will traverse.

Exceptions—Includes various types of exception handlers (e.g., invokedfor various error conditions).

FIG. 2D is a block diagram of general purpose graphics processing unit(GPGPU) 270 that can be configured as a graphics processor and/orcompute accelerator, according to embodiments described herein. TheGPGPU 270 can interconnect with host processors (e.g., one or moreCPU(s) 246) and memory 271, 272 via one or more system and/or memorybusses. In one embodiment the memory 271 is system memory that may beshared with the one or more CPU(s) 246, while memory 272 is devicememory that is dedicated to the GPGPU 270. In one embodiment, componentswithin the GPGPU 270 and device memory 272 may be mapped into memoryaddresses that are accessible to the one or more CPU(s) 246. Access tomemory 271 and 272 may be facilitated via a memory controller 268. Inone embodiment the memory controller 268 includes an internal directmemory access (DMA) controller 269 or can include logic to performoperations that would otherwise be performed by a DMA controller.

The GPGPU 270 includes multiple cache memories, including an L2 cache253, L1 cache 254, an instruction cache 255, and shared memory 256, atleast a portion of which may also be partitioned as a cache memory. TheGPGPU 270 also includes multiple compute units 260A-260N. Each computeunit 260A-260N includes a set of vector registers 261, scalar registers262, vector logic units 263, and scalar logic units 264. The computeunits 260A-260N can also include local shared memory 265 and a programcounter 266. The compute units 260A-260N can couple with a constantcache 267, which can be used to store constant data, which is data thatwill not change during the run of kernel or shader program that executeson the GPGPU 270. In one embodiment the constant cache 267 is a scalardata cache and cached data can be fetched directly into the scalarregisters 262.

During operation, the one or more CPU(s) 246 can write commands intoregisters or memory in the GPGPU 270 that has been mapped into anaccessible address space. The command processors 257 can read thecommands from registers or memory and determine how those commands willbe processed within the GPGPU 270. A thread dispatcher 258 can then beused to dispatch threads to the compute units 260A-260N to perform thosecommands Each compute unit 260A-260N can execute threads independentlyof the other compute units. Additionally each compute unit 260A-260N canbe independently configured for conditional computation and canconditionally output the results of computation to memory. The commandprocessors 257 can interrupt the one or more CPU(s) 246 when thesubmitted commands are complete.

FIGS. 3A-3C illustrate block diagrams of additional graphics processorand compute accelerator architectures provided by embodiments describedherein. The elements of FIGS. 3A-3C having the same reference numbers(or names) as the elements of any other figure herein can operate orfunction in any manner similar to that described elsewhere herein, butare not limited to such.

FIG. 3A is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores, or other semiconductordevices such as, but not limited to, memory devices or networkinterfaces. In some embodiments, the graphics processor communicates viaa memory mapped I/O interface to registers on the graphics processor andwith commands placed into the processor memory. In some embodiments,graphics processor 300 includes a memory interface 314 to access memory.Memory interface 314 can be an interface to local memory, one or moreinternal caches, one or more shared external caches, and/or to systemmemory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 318.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. The display device 318 can be an internal orexternal display device. In one embodiment the display device 318 is ahead mounted display device, such as a virtual reality (VR) displaydevice or an augmented reality (AR) display device. In some embodiments,graphics processor 300 includes a video codec engine 306 to encode,decode, or transcode media to, from, or between one or more mediaencoding formats, including, but not limited to Moving Picture ExpertsGroup (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formatssuch as H.264/MPEG-4 AVC, H.265/HEVC, Alliance for Open Media (AOMedia)VP8, VP9, as well as the Society of Motion Picture & TelevisionEngineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG)formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 310. In someembodiments, GPE 310 is a compute engine for performing graphicsoperations, including three-dimensional (3D) graphics operations andmedia operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

FIG. 3B illustrates a graphics processor 320 having a tiledarchitecture, according to embodiments described herein. In oneembodiment the graphics processor 320 includes a graphics processingengine cluster 322 having multiple instances of the graphics processingengine 310 of FIG. 3A within a graphics engine tile 310A-310D. Eachgraphics engine tile 310A-310D can be interconnected via a set of tileinterconnects 323A-323F. Each graphics engine tile 310A-310D can also beconnected to a memory module or memory device 326A-326D via memoryinterconnects 325A-325D. The memory devices 326A-326D can use anygraphics memory technology. For example, the memory devices 326A-326Dmay be graphics double data rate (GDDR) memory. The memory devices326A-326D, in one embodiment, are high-bandwidth memory (HBM) modulesthat can be on-die with their respective graphics engine tile 310A-310D.In one embodiment the memory devices 326A-326D are stacked memorydevices that can be stacked on top of their respective graphics enginetile 310A-310D. In one embodiment, each graphics engine tile 310A-310Dand associated memory 326A-326D reside on separate chiplets, which arebonded to a base die or base substrate, as described on further detailin FIGS. 11B-11D.

The graphics processing engine cluster 322 can connect with an on-chipor on-package fabric interconnect 324. The fabric interconnect 324 canenable communication between graphics engine tiles 310A-310D andcomponents such as the video codec 306 and one or more copy engines 304.The copy engines 304 can be used to move data out of, into, and betweenthe memory devices 326A-326D and memory that is external to the graphicsprocessor 320 (e.g., system memory). The fabric interconnect 324 canalso be used to interconnect the graphics engine tiles 310A-310D. Thegraphics processor 320 may optionally include a display controller 302to enable a connection with an external display device 318. The graphicsprocessor may also be configured as a graphics or compute accelerator.In the accelerator configuration, the display controller 302 and displaydevice 318 may be omitted.

The graphics processor 320 can connect to a host system via a hostinterface 328. The host interface 328 can enable communication betweenthe graphics processor 320, system memory, and/or other systemcomponents. The host interface 328 can be, for example a PCI express busor another type of host system interface.

FIG. 3C illustrates a compute accelerator 330, according to embodimentsdescribed herein. The compute accelerator 330 can include architecturalsimilarities with the graphics processor 320 of FIG. 3B and is optimizedfor compute acceleration. A compute engine cluster 332 can include a setof compute engine tiles 340A-340D that include execution logic that isoptimized for parallel or vector-based general-purpose computeoperations. In some embodiments, the compute engine tiles 340A-340D donot include fixed function graphics processing logic, although in oneembodiment one or more of the compute engine tiles 340A-340D can includelogic to perform media acceleration. The compute engine tiles 340A-340Dcan connect to memory 326A-326D via memory interconnects 325A-325D. Thememory 326A-326D and memory interconnects 325A-325D may be similartechnology as in graphics processor 320, or can be different. Thegraphics compute engine tiles 340A-340D can also be interconnected via aset of tile interconnects 323A-323F and may be connected with and/orinterconnected by a fabric interconnect 324. In one embodiment thecompute accelerator 330 includes a large L3 cache 336 that can beconfigured as a device-wide cache. The compute accelerator 330 can alsoconnect to a host processor and memory via a host interface 328 in asimilar manner as the graphics processor 320 of FIG. 3B.

Graphics Processing Engine

FIG. 4 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the graphics processing engine (GPE) 410 is a version of theGPE 310 shown in FIG. 3A, and may also represent a graphics engine tile310A-310D of FIG. 3B. Elements of FIG. 4 having the same referencenumbers (or names) as the elements of any other figure herein canoperate or function in any manner similar to that described elsewhereherein, but are not limited to such. For example, the 3D pipeline 312and media pipeline 316 of FIG. 3A are illustrated. The media pipeline316 is optional in some embodiments of the GPE 410 and may not beexplicitly included within the GPE 410. For example and in at least oneembodiment, a separate media and/or image processor is coupled to theGPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer403, which provides a command stream to the 3D pipeline 312 and/or mediapipelines 316. In some embodiments, command streamer 403 is coupled withmemory, which can be system memory, or one or more of internal cachememory and shared cache memory. In some embodiments, command streamer403 receives commands from the memory and sends the commands to 3Dpipeline 312 and/or media pipeline 316. The commands are directivesfetched from a ring buffer, which stores commands for the 3D pipeline312 and media pipeline 316. In one embodiment, the ring buffer canadditionally include batch command buffers storing batches of multiplecommands. The commands for the 3D pipeline 312 can also includereferences to data stored in memory, such as but not limited to vertexand geometry data for the 3D pipeline 312 and/or image data and memoryobjects for the media pipeline 316. The 3D pipeline 312 and mediapipeline 316 process the commands and data by performing operations vialogic within the respective pipelines or by dispatching one or moreexecution threads to a graphics core array 414. In one embodiment thegraphics core array 414 include one or more blocks of graphics cores(e.g., graphics core(s) 415A, graphics core(s) 415B), each blockincluding one or more graphics cores. Each graphics core includes a setof graphics execution resources that includes general-purpose andgraphics specific execution logic to perform graphics and computeoperations, as well as fixed function texture processing and/or machinelearning and artificial intelligence acceleration logic.

In various embodiments the 3D pipeline 312 can include fixed functionand programmable logic to process one or more shader programs, such asvertex shaders, geometry shaders, pixel shaders, fragment shaders,compute shaders, or other shader programs, by processing theinstructions and dispatching execution threads to the graphics corearray 414. The graphics core array 414 provides a unified block ofexecution resources for use in processing these shader programs.Multi-purpose execution logic (e.g., execution units) within thegraphics core(s) 415A-414B of the graphic core array 414 includessupport for various 3D API shader languages and can execute multiplesimultaneous execution threads associated with multiple shaders.

In some embodiments, the graphics core array 414 includes executionlogic to perform media functions, such as video and/or image processing.In one embodiment, the execution units include general-purpose logicthat is programmable to perform parallel general-purpose computationaloperations, in addition to graphics processing operations. Thegeneral-purpose logic can perform processing operations in parallel orin conjunction with general-purpose logic within the processor core(s)107 of FIG. 1 or core 202A-202N as in FIG. 2A.

Output data generated by threads executing on the graphics core array414 can output data to memory in a unified return buffer (URB) 418. TheURB 418 can store data for multiple threads. In some embodiments the URB418 may be used to send data between different threads executing on thegraphics core array 414. In some embodiments the URB 418 mayadditionally be used for synchronization between threads on the graphicscore array and fixed function logic within the shared function logic420.

In some embodiments, graphics core array 414 is scalable, such that thearray includes a variable number of graphics cores, each having avariable number of execution units based on the target power andperformance level of GPE 410. In one embodiment the execution resourcesare dynamically scalable, such that execution resources may be enabledor disabled as needed.

The graphics core array 414 couples with shared function logic 420 thatincludes multiple resources that are shared between the graphics coresin the graphics core array. The shared functions within the sharedfunction logic 420 are hardware logic units that provide specializedsupplemental functionality to the graphics core array 414. In variousembodiments, shared function logic 420 includes but is not limited tosampler 421, math 422, and inter-thread communication (ITC) 423 logic.Additionally, some embodiments implement one or more cache(s) 425 withinthe shared function logic 420.

A shared function is implemented at least in a case where the demand fora given specialized function is insufficient for inclusion within thegraphics core array 414. Instead a single instantiation of thatspecialized function is implemented as a stand-alone entity in theshared function logic 420 and shared among the execution resourceswithin the graphics core array 414. The precise set of functions thatare shared between the graphics core array 414 and included within thegraphics core array 414 varies across embodiments. In some embodiments,specific shared functions within the shared function logic 420 that areused extensively by the graphics core array 414 may be included withinshared function logic 416 within the graphics core array 414. In variousembodiments, the shared function logic 416 within the graphics corearray 414 can include some or all logic within the shared function logic420. In one embodiment, all logic elements within the shared functionlogic 420 may be duplicated within the shared function logic 416 of thegraphics core array 414. In one embodiment the shared function logic 420is excluded in favor of the shared function logic 416 within thegraphics core array 414.

Execution Units

FIGS. 5A-5B illustrate thread execution logic 500 including an array ofprocessing elements employed in a graphics processor core according toembodiments described herein. Elements of FIGS. 5A-5B having the samereference numbers (or names) as the elements of any other figure hereincan operate or function in any manner similar to that describedelsewhere herein, but are not limited to such. FIG. 5A-5B illustrates anoverview of thread execution logic 500, which may be representative ofhardware logic illustrated with each sub-core 221A-221F of FIG. 2B. FIG.5A is representative of an execution unit within a general-purposegraphics processor, while FIG. 5B is representative of an execution unitthat may be used within a compute accelerator.

As illustrated in FIG. 5A, in some embodiments thread execution logic500 includes a shader processor 502, a thread dispatcher 504,instruction cache 506, a scalable execution unit array including aplurality of execution units 508A-508N, a sampler 510, shared localmemory 511, a data cache 512, and a data port 514. In one embodiment thescalable execution unit array can dynamically scale by enabling ordisabling one or more execution units (e.g., any of execution units508A, 508B, 508C, 508D, through 508N-1 and 508N) based on thecomputational requirements of a workload. In one embodiment the includedcomponents are interconnected via an interconnect fabric that links toeach of the components. In some embodiments, thread execution logic 500includes one or more connections to memory, such as system memory orcache memory, through one or more of instruction cache 506, data port514, sampler 510, and execution units 508A-508N. In some embodiments,each execution unit (e.g. 508A) is a stand-alone programmablegeneral-purpose computational unit that is capable of executing multiplesimultaneous hardware threads while processing multiple data elements inparallel for each thread. In various embodiments, the array of executionunits 508A-508N is scalable to include any number individual executionunits.

In some embodiments, the execution units 508A-508N are primarily used toexecute shader programs. A shader processor 502 can process the variousshader programs and dispatch execution threads associated with theshader programs via a thread dispatcher 504. In one embodiment thethread dispatcher includes logic to arbitrate thread initiation requestsfrom the graphics and media pipelines and instantiate the requestedthreads on one or more execution unit in the execution units 508A-508N.For example, a geometry pipeline can dispatch vertex, tessellation, orgeometry shaders to the thread execution logic for processing. In someembodiments, thread dispatcher 504 can also process runtime threadspawning requests from the executing shader programs.

In some embodiments, the execution units 508A-508N support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. The execution units support vertex and geometry processing(e.g., vertex programs, geometry programs, vertex shaders), pixelprocessing (e.g., pixel shaders, fragment shaders) and general-purposeprocessing (e.g., compute and media shaders). Each of the executionunits 508A-508N is capable of multi-issue single instruction multipledata (SIMD) execution and multi-threaded operation enables an efficientexecution environment in the face of higher latency memory accesses.Each hardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state.Execution is multi-issue per clock to pipelines capable of integer,single and double precision floating point operations, SIMD branchcapability, logical operations, transcendental operations, and othermiscellaneous operations. While waiting for data from memory or one ofthe shared functions, dependency logic within the execution units508A-508N causes a waiting thread to sleep until the requested data hasbeen returned. While the waiting thread is sleeping, hardware resourcesmay be devoted to processing other threads. For example, during a delayassociated with a vertex shader operation, an execution unit can performoperations for a pixel shader, fragment shader, or another type ofshader program, including a different vertex shader. Various embodimentscan apply to use execution by use of Single Instruction Multiple Thread(SIMT) as an alternate to use of SIMD or in addition to use of SIMD.Reference to a SIMD core or operation can apply also to SIMT or apply toSIMD in combination with SIMT.

Each execution unit in execution units 508A-508N operates on arrays ofdata elements. The number of data elements is the “execution size,” orthe number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 508A-508N support integer andfloating-point data types.

The execution unit instruction set includes SIMD instructions. Thevarious data elements can be stored as a packed data type in a registerand the execution unit will process the various elements based on thedata size of the elements. For example, when operating on a 256-bit widevector, the 256 bits of the vector are stored in a register and theexecution unit operates on the vector as four separate 54-bit packeddata elements (Quad-Word (QW) size data elements), eight separate 32-bitpacked data elements (Double Word (DW) size data elements), sixteenseparate 16-bit packed data elements (Word (W) size data elements), orthirty-two separate 8-bit data elements (byte (B) size data elements).However, different vector widths and register sizes are possible.

In one embodiment one or more execution units can be combined into afused execution unit 509A-509N having thread control logic (507A-507N)that is common to the fused EUs. Multiple EUs can be fused into an EUgroup. Each EU in the fused EU group can be configured to execute aseparate SIMD hardware thread. The number of EUs in a fused EU group canvary according to embodiments. Additionally, various SIMD widths can beperformed per-EU, including but not limited to SIMD8, SIMD16, andSIMD32. Each fused graphics execution unit 509A-509N includes at leasttwo execution units. For example, fused execution unit 509A includes afirst EU 508A, second EU 508B, and thread control logic 507A that iscommon to the first EU 508A and the second EU 508B. The thread controllogic 507A controls threads executed on the fused graphics executionunit 509A, allowing each EU within the fused execution units 509A-509Nto execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 506) are included in thethread execution logic 500 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,512) are included to cache thread data during thread execution. Threadsexecuting on the execution logic 500 can also store explicitly manageddata in the shared local memory 511. In some embodiments, a sampler 510is included to provide texture sampling for 3D operations and mediasampling for media operations. In some embodiments, sampler 510 includesspecialized texture or media sampling functionality to process textureor media data during the sampling process before providing the sampleddata to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 500 via thread spawningand dispatch logic. Once a group of geometric objects has been processedand rasterized into pixel data, pixel processor logic (e.g., pixelshader logic, fragment shader logic, etc.) within the shader processor502 is invoked to further compute output information and cause resultsto be written to output surfaces (e.g., color buffers, depth buffers,stencil buffers, etc.). In some embodiments, a pixel shader or fragmentshader calculates the values of the various vertex attributes that areto be interpolated across the rasterized object. In some embodiments,pixel processor logic within the shader processor 502 then executes anapplication programming interface (API)-supplied pixel or fragmentshader program. To execute the shader program, the shader processor 502dispatches threads to an execution unit (e.g., 508A) via threaddispatcher 504. In some embodiments, shader processor 502 uses texturesampling logic in the sampler 510 to access texture data in texture mapsstored in memory. Arithmetic operations on the texture data and theinput geometry data compute pixel color data for each geometricfragment, or discards one or more pixels from further processing.

In some embodiments, the data port 514 provides a memory accessmechanism for the thread execution logic 500 to output processed data tomemory for further processing on a graphics processor output pipeline.In some embodiments, the data port 514 includes or couples to one ormore cache memories (e.g., data cache 512) to cache data for memoryaccess via the data port.

In one embodiment, the execution logic 500 can also include a ray tracer505 that can provide ray tracing acceleration functionality. The raytracer 505 can support a ray tracing instruction set that includesinstructions/functions for ray generation. The ray tracing instructionset can be similar to or different from the ray-tracing instruction setsupported by the ray tracing cores 245 in FIG. 2C.

FIG. 5B illustrates exemplary internal details of an execution unit 508,according to embodiments. A graphics execution unit 508 can include aninstruction fetch unit 537, a general register file array (GRF) 524, anarchitectural register file array (ARF) 526, a thread arbiter 522, asend unit 530, a branch unit 532, a set of SIMD floating point units(FPUs) 534, and in one embodiment a set of dedicated integer SIMD ALUs535. The GRF 524 and ARF 526 includes the set of general register filesand architecture register files associated with each simultaneoushardware thread that may be active in the graphics execution unit 508.In one embodiment, per thread architectural state is maintained in theARF 526, while data used during thread execution is stored in the GRF524. The execution state of each thread, including the instructionpointers for each thread, can be held in thread-specific registers inthe ARF 526.

In one embodiment the graphics execution unit 508 has an architecturethat is a combination of Simultaneous Multi-Threading (SMT) andfine-grained Interleaved Multi-Threading (IMT). The architecture has amodular configuration that can be fine-tuned at design time based on atarget number of simultaneous threads and number of registers perexecution unit, where execution unit resources are divided across logicused to execute multiple simultaneous threads. The number of logicalthreads that may be executed by the graphics execution unit 508 is notlimited to the number of hardware threads, and multiple logical threadscan be assigned to each hardware thread.

In one embodiment, the graphics execution unit 508 can co-issue multipleinstructions, which may each be different instructions. The threadarbiter 522 of the graphics execution unit thread 508 can dispatch theinstructions to one of the send unit 530, branch unit 532, or SIMDFPU(s) 534 for execution. Each execution thread can access 128general-purpose registers within the GRF 524, where each register canstore 32 bytes, accessible as a SIMD 8-element vector of 32-bit dataelements. In one embodiment, each execution unit thread has access to 4Kbytes within the GRF 524, although embodiments are not so limited, andgreater or fewer register resources may be provided in otherembodiments. In one embodiment the graphics execution unit 508 ispartitioned into seven hardware threads that can independently performcomputational operations, although the number of threads per executionunit can also vary according to embodiments. For example, in oneembodiment up to 16 hardware threads are supported. In an embodiment inwhich seven threads may access 4 Kbytes, the GRF 524 can store a totalof 28 Kbytes. Where 16 threads may access 4 Kbytes, the GRF 524 canstore a total of 64 Kbytes. Flexible addressing modes can permitregisters to be addressed together to build effectively wider registersor to represent strided rectangular block data structures.

In one embodiment, memory operations, sampler operations, and otherlonger-latency system communications are dispatched via “send”instructions that are executed by the message passing send unit 530. Inone embodiment, branch instructions are dispatched to a dedicated branchunit 532 to facilitate SIMD divergence and eventual convergence.

In one embodiment the graphics execution unit 508 includes one or moreSIMD floating point units (FPU(s)) 534 to perform floating-pointoperations. In one embodiment, the FPU(s) 534 also support integercomputation. In one embodiment the FPU(s) 534 can SIMD execute up to Mnumber of 32-bit floating-point (or integer) operations, or SIMD executeup to 2M 16-bit integer or 16-bit floating-point operations. In oneembodiment, at least one of the FPU(s) provides extended math capabilityto support high-throughput transcendental math functions and doubleprecision 54-bit floating-point. In some embodiments, a set of 8-bitinteger SIMD ALUs 535 are also present, and may be specificallyoptimized to perform operations associated with machine learningcomputations.

In one embodiment, arrays of multiple instances of the graphicsexecution unit 508 can be instantiated in a graphics sub-core grouping(e.g., a sub-slice). For scalability, product architects can choose theexact number of execution units per sub-core grouping. In one embodimentthe execution unit 508 can execute instructions across a plurality ofexecution channels. In a further embodiment, each thread executed on thegraphics execution unit 508 is executed on a different channel.

FIG. 6 illustrates an additional execution unit 600, according to anembodiment. The execution unit 600 may be a compute-optimized executionunit for use in, for example, a compute engine tile 340A-340D as in FIG.3C, but is not limited as such. Variants of the execution unit 600 mayalso be used in a graphics engine tile 310A-310D as in FIG. 3B. In oneembodiment, the execution unit 600 includes a thread control unit 601, athread state unit 602, an instruction fetch/prefetch unit 603, and aninstruction decode unit 604. The execution unit 600 additionallyincludes a register file 606 that stores registers that can be assignedto hardware threads within the execution unit. The execution unit 600additionally includes a send unit 607 and a branch unit 608. In oneembodiment, the send unit 607 and branch unit 608 can operate similarlyas the send unit 530 and a branch unit 532 of the graphics executionunit 508 of FIG. 5B.

The execution unit 600 also includes a compute unit 610 that includesmultiple different types of functional units. In one embodiment thecompute unit 610 includes an ALU unit 611 that includes an array ofarithmetic logic units. The ALU unit 611 can be configured to perform64-bit, 32-bit, and 16-bit integer and floating point operations.Integer and floating point operations may be performed simultaneously.The compute unit 610 can also include a systolic array 612, and a mathunit 613. The systolic array 612 includes a W wide and D deep network ofdata processing units that can be used to perform vector or otherdata-parallel operations in a systolic manner In one embodiment thesystolic array 612 can be configured to perform matrix operations, suchas matrix dot product operations. In one embodiment the systolic array612 support 16-bit floating point operations, as well as 8-bit and 4-bitinteger operations. In one embodiment the systolic array 612 can beconfigured to accelerate machine learning operations. In suchembodiments, the systolic array 612 can be configured with support forthe bfloat 16-bit floating point format. In one embodiment, a math unit613 can be included to perform a specific subset of mathematicaloperations in an efficient and lower-power manner than then ALU unit611. The math unit 613 can include a variant of math logic that may befound in shared function logic of a graphics processing engine providedby other embodiments (e.g., math logic 422 of the shared function logic420 of FIG. 4). In one embodiment the math unit 613 can be configured toperform 32-bit and 64-bit floating point operations.

The thread control unit 601 includes logic to control the execution ofthreads within the execution unit. The thread control unit 601 caninclude thread arbitration logic to start, stop, and preempt executionof threads within the execution unit 600. The thread state unit 602 canbe used to store thread state for threads assigned to execute on theexecution unit 600. Storing the thread state within the execution unit600 enables the rapid pre-emption of threads when those threads becomeblocked or idle. The instruction fetch/prefetch unit 603 can fetchinstructions from an instruction cache of higher level execution logic(e.g., instruction cache 506 as in FIG. 5A). The instructionfetch/prefetch unit 603 can also issue prefetch requests forinstructions to be loaded into the instruction cache based on ananalysis of currently executing threads. The instruction decode unit 604can be used to decode instructions to be executed by the compute units.In one embodiment, the instruction decode unit 604 can be used as asecondary decoder to decode complex instructions into constituentmicro-operations.

The execution unit 600 additionally includes a register file 606 thatcan be used by hardware threads executing on the execution unit 600.Registers in the register file 606 can be divided across the logic usedto execute multiple simultaneous threads within the compute unit 610 ofthe execution unit 600. The number of logical threads that may beexecuted by the graphics execution unit 600 is not limited to the numberof hardware threads, and multiple logical threads can be assigned toeach hardware thread. The size of the register file 606 can vary acrossembodiments based on the number of supported hardware threads. In oneembodiment, register renaming may be used to dynamically allocateregisters to hardware threads.

FIG. 7 is a block diagram illustrating a graphics processor instructionformats 700 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments,instruction format 700 described and illustrated are macro-instructions,in that they are instructions supplied to the execution unit, as opposedto micro-operations resulting from instruction decode once theinstruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit instruction format 710. A 64-bitcompacted instruction format 730 is available for some instructionsbased on the selected instruction, instruction options, and number ofoperands. The native 128-bit instruction format 710 provides access toall instruction options, while some options and operations arerestricted in the 64-bit format 730. The native instructions availablein the 64-bit format 730 vary by embodiment. In some embodiments, theinstruction is compacted in part using a set of index values in an indexfield 713. The execution unit hardware references a set of compactiontables based on the index values and uses the compaction table outputsto reconstruct a native instruction in the 128-bit instruction format710. Other sizes and formats of instruction can be used.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 714 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). Forinstructions in the 128-bit instruction format 710 an exec-size field716 limits the number of data channels that will be executed inparallel. In some embodiments, exec-size field 716 is not available foruse in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 720, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode 712 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726 specifying, for example, whether directregister addressing mode or indirect register addressing mode is used.When direct register addressing mode is used, the register address ofone or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726, which specifies an address mode and/or anaccess mode for the instruction. In one embodiment the access mode isused to define a data access alignment for the instruction. Someembodiments support access modes including a 16-byte aligned access modeand a 1-byte aligned access mode, where the byte alignment of the accessmode determines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction may use 16-byte-aligned addressing for all sourceand destination operands.

In one embodiment, the address mode portion of the access/address modefield 726 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction directly provide the register address of one or moreoperands. When indirect register addressing mode is used, the registeraddress of one or more operands may be computed based on an addressregister value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 742 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 742 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 744 (e.g., call, jump (jmp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes amix of instructions, including synchronization instructions (e.g., wait,send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instructiongroup 748 includes component-wise arithmetic instructions (e.g., add,multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel mathgroup 748 performs the arithmetic operations in parallel across datachannels. The vector math group 750 includes arithmetic instructions(e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math groupperforms arithmetic such as dot product calculations on vector operands.The illustrated opcode decode 740, in one embodiment, can be used todetermine which portion of an execution unit will be used to execute adecoded instruction. For example, some instructions may be designated assystolic instructions that will be performed by a systolic array. Otherinstructions, such as ray-tracing instructions (not shown) can be routedto a ray-tracing core or ray-tracing logic within a slice or partitionof execution logic.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor800. Elements of FIG. 8 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 800 includes a geometry pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general-purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of the geometry pipeline 820 or the media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A-852B via a thread dispatcher831.

In some embodiments, execution units 852A-852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A-852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, geometry pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to geometry pipeline 820. Insome embodiments, if tessellation is not used, tessellation components(e.g., hull shader 811, tessellator 813, and domain shader 817) can bebypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A-852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper829 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer and depth test component 873 in the render output pipeline870 dispatches pixel shaders to convert the geometric objects into perpixel representations. In some embodiments, pixel shader logic isincluded in thread execution logic 850. In some embodiments, anapplication can bypass the rasterizer and depth test component 873 andaccess un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A-852B and associated logic units (e.g.,L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via adata port 856 to perform memory access and communicate with renderoutput pipeline components of the processor. In some embodiments,sampler 854, caches 851, 858 and execution units 852A-852B each haveseparate memory access paths. In one embodiment the texture cache 858can also be configured as a sampler cache.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache 878and depth cache 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 837 and a video front-end 834. In some embodiments, videofront-end 834 receives pipeline commands from the command streamer 803.In some embodiments, media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 837 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, the geometry pipeline 820 and media pipeline 830are configurable to perform operations based on multiple graphics andmedia programming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL), Open Computing Language (OpenCL),and/or Vulkan graphics and compute API, all from the Khronos Group. Insome embodiments, support may also be provided for the Direct3D libraryfrom the Microsoft Corporation. In some embodiments, a combination ofthese libraries may be supported. Support may also be provided for theOpen Source Computer Vision Library (OpenCV). A future API with acompatible 3D pipeline would also be supported if a mapping can be madefrom the pipeline of the future API to the pipeline of the graphicsprocessor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 9B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. The solid lined boxes in FIG. 9A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 900 of FIG. 9A includes data fields to identify a client902, a command operation code (opcode) 904, and data 906 for the commandA sub-opcode 905 and a command size 908 are also included in somecommands.

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands Oncethe command is received by the client unit, the client unit reads theopcode 904 and, if present, sub-opcode 905 to determine the operation toperform. The client unit performs the command using information in datafield 906. For some commands an explicit command size 908 is expected tospecify the size of the command In some embodiments, the command parserautomatically determines the size of at least some of the commands basedon the command opcode. In some embodiments commands are aligned viamultiples of a double word. Other command formats can be used.

The flow diagram in FIG. 9B illustrates an exemplary graphics processorcommand sequence 910. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 maybegin with a pipeline flush command 912 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands In response toa pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command 912 is required immediatelybefore a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 916 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 916 includes selecting the size and number of returnbuffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930 or the media pipeline 924 beginning at themedia pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D statesetting commands for vertex buffer state, vertex element state, constantcolor state, depth buffer state, and other state variables that are tobe configured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based on the particular3D API in use. In some embodiments, 3D pipeline state 930 commands arealso able to selectively disable or bypass certain pipeline elements ifthose elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment, commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 910 followsthe media pipeline 924 path when performing media operations. Ingeneral, the specific use and manner of programming for the mediapipeline 924 depends on the media or compute operations to be performed.Specific media decode operations may be offloaded to the media pipelineduring media decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general-purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of commands to configure the mediapipeline state 940 are dispatched or placed into a command queue beforethe media object commands 942. In some embodiments, commands for themedia pipeline state 940 include data to configure the media pipelineelements that will be used to process the media objects. This includesdata to configure the video decode and video encode logic within themedia pipeline, such as encode or decode format. In some embodiments,commands for the media pipeline state 940 also support the use of one ormore pointers to “indirect” state elements that contain a batch of statesettings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia object commands 942 are queued, the media pipeline 924 istriggered via an execute command 944 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates an exemplary graphics software architecture for adata processing system 1000 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application1010, an operating system 1020, and at least one processor 1030. In someembodiments, processor 1030 includes a graphics processor 1032 and oneor more general-purpose processor core(s) 1034. The graphics application1010 and operating system 1020 each execute in the system memory 1050 ofthe data processing system.

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as theHigh-Level Shader Language (HLSL) of Direct3D, the OpenGL ShaderLanguage (GLSL), and so forth. The application also includes executableinstructions 1014 in a machine language suitable for execution by thegeneral-purpose processor core 1034. The application also includesgraphics objects 1016 defined by vertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. The operating system 1020 can support agraphics API 1022 such as the Direct3D API, the OpenGL API, or theVulkan API. When the Direct3D API is in use, the operating system 1020uses a front-end shader compiler 1024 to compile any shader instructions1012 in HLSL into a lower-level shader language. The compilation may bea just-in-time (JIT) compilation or the application can perform shaderpre-compilation. In some embodiments, high-level shaders are compiledinto low-level shaders during the compilation of the 3D graphicsapplication 1010. In some embodiments, the shader instructions 1012 areprovided in an intermediate form, such as a version of the StandardPortable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 11A is a block diagram illustrating an IP core development system1100 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system1100 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility1130 can generate a software simulation 1110 of an IP core design in ahigh-level programming language (e.g., C/C++). The software simulation1110 can be used to design, test, and verify the behavior of the IP coreusing a simulation model 1112. The simulation model 1112 may includefunctional, behavioral, and/or timing simulations. A register transferlevel (RTL) design 1115 can then be created or synthesized from thesimulation model 1112. The RTL design 1115 is an abstraction of thebehavior of the integrated circuit that models the flow of digitalsignals between hardware registers, including the associated logicperformed using the modeled digital signals. In addition to an RTLdesign 1115, lower-level designs at the logic level or transistor levelmay also be created, designed, or synthesized. Thus, the particulardetails of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by thedesign facility into a hardware model 1120, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3rdparty fabrication facility 1165 using non-volatile memory 1140 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 1150 or wireless connection 1160. Thefabrication facility 1165 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

FIG. 11B illustrates a cross-section side view of an integrated circuitpackage assembly 1170, according to some embodiments described herein.The integrated circuit package assembly 1170 illustrates animplementation of one or more processor or accelerator devices asdescribed herein. The package assembly 1170 includes multiple units ofhardware logic 1172, 1174 connected to a substrate 1180. The logic 1172,1174 may be implemented at least partly in configurable logic orfixed-functionality logic hardware, and can include one or more portionsof any of the processor core(s), graphics processor(s), or otheraccelerator devices described herein. Each unit of logic 1172, 1174 canbe implemented within a semiconductor die and coupled with the substrate1180 via an interconnect structure 1173. The interconnect structure 1173may be configured to route electrical signals between the logic 1172,1174 and the substrate 1180, and can include interconnects such as, butnot limited to bumps or pillars. In some embodiments, the interconnectstructure 1173 may be configured to route electrical signals such as,for example, input/output (I/O) signals and/or power or ground signalsassociated with the operation of the logic 1172, 1174. In someembodiments, the substrate 1180 is an epoxy-based laminate substrate.The substrate 1180 may include other suitable types of substrates inother embodiments. The package assembly 1170 can be connected to otherelectrical devices via a package interconnect 1183. The packageinterconnect 1183 may be coupled to a surface of the substrate 1180 toroute electrical signals to other electrical devices, such as amotherboard, other chipset, or multi-chip module.

In some embodiments, the units of logic 1172, 1174 are electricallycoupled with a bridge 1182 that is configured to route electricalsignals between the logic 1172, 1174. The bridge 1182 may be a denseinterconnect structure that provides a route for electrical signals. Thebridge 1182 may include a bridge substrate composed of glass or asuitable semiconductor material. Electrical routing features can beformed on the bridge substrate to provide a chip-to-chip connectionbetween the logic 1172, 1174.

Although two units of logic 1172, 1174 and a bridge 1182 areillustrated, embodiments described herein may include more or fewerlogic units on one or more dies. The one or more dies may be connectedby zero or more bridges, as the bridge 1182 may be excluded when thelogic is included on a single die. Alternatively, multiple dies or unitsof logic can be connected by one or more bridges. Additionally, multiplelogic units, dies, and bridges can be connected together in otherpossible configurations, including three-dimensional configurations.

FIG. 11C illustrates a package assembly 1190 that includes multipleunits of hardware logic chiplets connected to a substrate 1180 (e.g.,base die). A graphics processing unit, parallel processor, and/orcompute accelerator as described herein can be composed from diversesilicon chiplets that are separately manufactured. In this context, achiplet is an at least partially packaged integrated circuit thatincludes distinct units of logic that can be assembled with otherchiplets into a larger package. A diverse set of chiplets with differentIP core logic can be assembled into a single device. Additionally thechiplets can be integrated into a base die or base chiplet using activeinterposer technology. The concepts described herein enable theinterconnection and communication between the different forms of IPwithin the GPU. IP cores can be manufactured using different processtechnologies and composed during manufacturing, which avoids thecomplexity of converging multiple IPs, especially on a large SoC withseveral flavors IPs, to the same manufacturing process. Enabling the useof multiple process technologies improves the time to market andprovides a cost-effective way to create multiple product SKUs.Additionally, the disaggregated IPs are more amenable to being powergated independently, components that are not in use on a given workloadcan be powered off, reducing overall power consumption.

The hardware logic chiplets can include special purpose hardware logicchiplets 1172, logic or I/O chiplets 1174, and/or memory chiplets 1175.The hardware logic chiplets 1172 and logic or I/O chiplets 1174 may beimplemented at least partly in configurable logic or fixed-functionalitylogic hardware and can include one or more portions of any of theprocessor core(s), graphics processor(s), parallel processors, or otheraccelerator devices described herein. The memory chiplets 1175 can beDRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

Each chiplet can be fabricated as separate semiconductor die and coupledwith the substrate 1180 via an interconnect structure 1173. Theinterconnect structure 1173 may be configured to route electricalsignals between the various chiplets and logic within the substrate1180. The interconnect structure 1173 can include interconnects such as,but not limited to bumps or pillars. In some embodiments, theinterconnect structure 1173 may be configured to route electricalsignals such as, for example, input/output (I/O) signals and/or power orground signals associated with the operation of the logic, I/O andmemory chiplets.

In some embodiments, the substrate 1180 is an epoxy-based laminatesubstrate. The substrate 1180 may include other suitable types ofsubstrates in other embodiments. The package assembly 1190 can beconnected to other electrical devices via a package interconnect 1183.The package interconnect 1183 may be coupled to a surface of thesubstrate 1180 to route electrical signals to other electrical devices,such as a motherboard, other chipset, or multi-chip module.

In some embodiments, a logic or I/O chiplet 1174 and a memory chiplet1175 can be electrically coupled via a bridge 1187 that is configured toroute electrical signals between the logic or I/O chiplet 1174 and amemory chiplet 1175. The bridge 1187 may be a dense interconnectstructure that provides a route for electrical signals. The bridge 1187may include a bridge substrate composed of glass or a suitablesemiconductor material. Electrical routing features can be formed on thebridge substrate to provide a chip-to-chip connection between the logicor I/O chiplet 1174 and a memory chiplet 1175. The bridge 1187 may alsobe referred to as a silicon bridge or an interconnect bridge. Forexample, the bridge 1187, in some embodiments, is an Embedded Multi-dieInterconnect Bridge (EMIB). In some embodiments, the bridge 1187 maysimply be a direct connection from one chiplet to another chiplet.

The substrate 1180 can include hardware components for I/O 1191, cachememory 1192, and other hardware logic 1193. A fabric 1185 can beembedded in the substrate 1180 to enable communication between thevarious logic chiplets and the logic 1191, 1193 within the substrate1180. In one embodiment, the I/O 1191, fabric 1185, cache, bridge, andother hardware logic 1193 can be integrated into a base die that islayered on top of the substrate 1180.

In various embodiments a package assembly 1190 can include fewer orgreater number of components and chiplets that are interconnected by afabric 1185 or one or more bridges 1187. The chiplets within the packageassembly 1190 may be arranged in a 3D or 2.5D arrangement. In general,bridge structures 1187 may be used to facilitate a point to pointinterconnect between, for example, logic or I/O chiplets and memorychiplets. The fabric 1185 can be used to interconnect the various logicand/or I/O chiplets (e.g., chiplets 1172, 1174, 1191, 1193). with otherlogic and/or I/O chiplets. In one embodiment, the cache memory 1192within the substrate can act as a global cache for the package assembly1190, part of a distributed global cache, or as a dedicated cache forthe fabric 1185.

FIG. 11D illustrates a package assembly 1194 including interchangeablechiplets 1195, according to an embodiment. The interchangeable chiplets1195 can be assembled into standardized slots on one or more basechiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via abridge interconnect 1197, which can be similar to the other bridgeinterconnects described herein and may be, for example, an EMIB. Memorychiplets can also be connected to logic or I/O chiplets via a bridgeinterconnect. I/O and logic chiplets can communicate via an interconnectfabric. The base chiplets can each support one or more slots in astandardized format for one of logic or I/O or memory/cache.

In one embodiment, SRAM and power delivery circuits can be fabricatedinto one or more of the base chiplets 1196, 1198, which can befabricated using a different process technology relative to theinterchangeable chiplets 1195 that are stacked on top of the basechiplets. For example, the base chiplets 1196, 1198 can be fabricatedusing a larger process technology, while the interchangeable chipletscan be manufactured using a smaller process technology. One or more ofthe interchangeable chiplets 1195 may be memory (e.g., DRAM) chiplets.Different memory densities can be selected for the package assembly 1194based on the power, and/or performance targeted for the product thatuses the package assembly 1194. Additionally, logic chiplets with adifferent number of type of functional units can be selected at time ofassembly based on the power, and/or performance targeted for theproduct. Additionally, chiplets containing IP logic cores of differingtypes can be inserted into the interchangeable chiplet slots, enablinghybrid processor designs that can mix and match different technology IPblocks.

Exemplary System on a Chip Integrated Circuit

FIGS. 12-13 illustrate exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included, includingadditional graphics processors/cores, peripheral interface controllers,or general-purpose processor cores.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1200 that may be fabricated using one or more IPcores, according to an embodiment. Exemplary integrated circuit 1200includes one or more application processor(s) 1205 (e.g., CPUs), atleast one graphics processor 1210, and may additionally include an imageprocessor 1215 and/or a video processor 1220, any of which may be amodular IP core from the same or multiple different design facilities.Integrated circuit 1200 includes peripheral or bus logic including a USBcontroller 1225, UART controller 1230, an SPI/SDIO controller 1235, andan I2S/I2C controller 1240. Additionally, the integrated circuit caninclude a display device 1245 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 1250 and a mobileindustry processor interface (MIPI) display interface 1255. Storage maybe provided by a flash memory subsystem 1260 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 1265 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine1270.

FIGS. 13-14 are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to embodiments describedherein. FIG. 13 illustrates an exemplary graphics processor 1310 of asystem on a chip integrated circuit that may be fabricated using one ormore IP cores, according to an embodiment. FIG. 13B illustrates anadditional exemplary graphics processor 1340 of a system on a chipintegrated circuit that may be fabricated using one or more IP cores,according to an embodiment. Graphics processor 1310 of FIG. 13 is anexample of a low power graphics processor core. Graphics processor 1340of FIG. 13B is an example of a higher performance graphics processorcore. Each of the graphics processors 1310, 1340 can be variants of thegraphics processor 1210 of FIG. 12.

As shown in FIG. 13, graphics processor 1310 includes a vertex processor1305 and one or more fragment processor(s) 1315A-1315N (e.g., 1315A,1315B, 1315C, 1315D, through 1315N-1, and 1315N). Graphics processor1310 can execute different shader programs via separate logic, such thatthe vertex processor 1305 is optimized to execute operations for vertexshader programs, while the one or more fragment processor(s) 1315A-1315Nexecute fragment (e.g., pixel) shading operations for fragment or pixelshader programs. The vertex processor 1305 performs the vertexprocessing stage of the 3D graphics pipeline and generates primitivesand vertex data. The fragment processor(s) 1315A-1315N use the primitiveand vertex data generated by the vertex processor 1305 to produce aframebuffer that is displayed on a display device. In one embodiment,the fragment processor(s) 1315A-1315N are optimized to execute fragmentshader programs as provided for in the OpenGL API, which may be used toperform similar operations as a pixel shader program as provided for inthe Direct 3D API.

Graphics processor 1310 additionally includes one or more memorymanagement units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuitinterconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B providefor virtual to physical address mapping for the graphics processor 1310,including for the vertex processor 1305 and/or fragment processor(s)1315A-1315N, which may reference vertex or image/texture data stored inmemory, in addition to vertex or image/texture data stored in the one ormore cache(s) 1325A-1325B. In one embodiment the one or more MMU(s)1320A-1320B may be synchronized with other MMUs within the system,including one or more MMUs associated with the one or more applicationprocessor(s) 1205, image processor 1215, and/or video processor 1220 ofFIG. 12, such that each processor 1205-1220 can participate in a sharedor unified virtual memory system. The one or more circuitinterconnect(s) 1330A-1330B enable graphics processor 1310 to interfacewith other IP cores within the SoC, either via an internal bus of theSoC or via a direct connection, according to embodiments.

As shown FIG. 14, graphics processor 1340 includes the one or moreMMU(s) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s)1330A-1330B of the graphics processor 1310 of FIG. 13A. Graphicsprocessor 1340 includes one or more shader core(s) 1355A-1355N (e.g.,1455A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-1, and 1355N),which provides for a unified shader core architecture in which a singlecore or type or core can execute all types of programmable shader code,including shader program code to implement vertex shaders, fragmentshaders, and/or compute shaders. The exact number of shader corespresent can vary among embodiments and implementations. Additionally,graphics processor 1340 includes an inter-core task manager 1345, whichacts as a thread dispatcher to dispatch execution threads to one or moreshader cores 1355A-1355N and a tiling unit 1358 to accelerate tilingoperations for tile-based rendering, in which rendering operations for ascene are subdivided in image space, for example to exploit localspatial coherence within a scene or to optimize use of internal caches.

As indicated above, to quantize the vertex component to NV-bit signedspace, each vertex component's exponent is subtracted from the globalexponent for that axis. The component value is then shifted down by thisdifference. This may of course discard some precision in the lowerportion of the component. To capture this loss, an AABB is produced byrounding the min value down and the max value up after this shift. Tomaintain simplicity, a vertex is quantized to a unit AABB, even if thereis no error during quantization.

Ray Tracing Architecture

In one implementation, the graphics processor includes circuitry and/orprogram code for performing real-time ray tracing. In some embodiments,a dedicated set of ray tracing cores are included in the graphicsprocessor to perform the various ray tracing operations describedherein, including ray traversal and/or ray intersection operations. Inaddition to the ray tracing cores, one embodiment includes multiple setsof graphics processing cores for performing programmable shadingoperations and multiple sets of tensor cores for performing matrixoperations on tensor data.

FIG. 15 illustrates an exemplary portion of one such graphics processingunit (GPU) 1505 which includes dedicated sets of graphics processingresources arranged into multi-core groups 1500A-N. While the details ofonly a single multi-core group 1500A are provided, it will beappreciated that the other multi-core groups 1500B-N may be equippedwith the same or similar sets of graphics processing resources.

As illustrated, a multi-core group 1500A may include a set of graphicscores 1530, a set of tensor cores 1540, and a set of ray tracing cores1550. A scheduler/dispatcher 1510 schedules and dispatches the graphicsthreads for execution on the various cores 1530, 1540, 1550. A set ofregister files 1520 store operand values used by the cores 1530, 1540,1550 when executing the graphics threads. These may include, forexample, integer registers for storing integer values, floating pointregisters for storing floating point values, vector registers forstoring packed data elements (integer and/or floating point dataelements) and tile registers for storing tensor/matrix values. In oneembodiment, the tile registers are implemented as combined sets ofvector registers.

One or more Level 1 (L1) caches and texture units 1560 store graphicsdata such as texture data, vertex data, pixel data, ray data, boundingvolume data, etc, locally within each multi-core group 1500A. A Level 2(L2) cache 1580 shared by all or a subset of the multi-core groups1500A-N stores graphics data and/or instructions for multiple concurrentgraphics threads. As illustrated, the L2 cache 1580 may be shared acrossa plurality of multi-core groups 1500A-N. One or more memory controllers1570 couple the GPU 1505 to a memory 1598 which may be a system memory(e.g., DRAM) and/or a dedicated graphics memory (e.g., GDDR6 memory).

Input/output (IO) circuitry 1595 couples the GPU 1505 to one or more IOdevices 1595 such as digital signal processors (DSPs), networkcontrollers, or user input devices. An on-chip interconnect may be usedto couple the I/O devices 1590 to the GPU 1505 and memory 1598. One ormore IO memory management units (IOMMUs) 1570 of the IO circuitry 1595couple the IO devices 1590 directly to the system memory 1598. In oneembodiment, the IOMMU 1570 manages multiple sets of page tables to mapvirtual addresses to physical addresses in system memory 1598. In thisembodiment, the IO devices 1590, CPU(s) 1599, and GPU(s) 1505 may sharethe same virtual address space.

In one implementation, the IOMMU 1570 supports virtualization. In thiscase, it may manage a first set of page tables to map guest/graphicsvirtual addresses to guest/graphics physical addresses and a second setof page tables to map the guest/graphics physical addresses tosystem/host physical addresses (e.g., within system memory 1598). Thebase addresses of each of the first and second sets of page tables maybe stored in control registers and swapped out on a context switch(e.g., so that the new context is provided with access to the relevantset of page tables). While not illustrated in FIG. 15, each of the cores1530, 1540, 1550 and/or multi-core groups 1500A-N may includetranslation lookaside buffers (TLBs) to cache guest virtual to guestphysical translations, guest physical to host physical translations, andguest virtual to host physical translations.

In one embodiment, the CPUs 1599, GPUs 1505, and IO devices 1590 areintegrated on a single semiconductor chip and/or chip package. Theillustrated memory 1598 may be integrated on the same chip or may becoupled to the memory controllers 1570 via an off-chip interface. In oneimplementation, the memory 1598 comprises GDDR6 memory which shares thesame virtual address space as other physical system-level memories,although the underlying principles of the invention are not limited tothis specific implementation.

In one embodiment, the tensor cores 1540 include a plurality ofexecution units specifically designed to perform matrix operations,which are the fundamental compute operation used to perform deeplearning operations. For example, simultaneous matrix multiplicationoperations may be used for neural network training and inferencing. Thetensor cores 1540 may perform matrix processing using a variety ofoperand precisions including single precision floating-point (e.g., 32bits), half-precision floating point (e.g., 16 bits), integer words (16bits), bytes (8 bits), and half-bytes (4 bits). In one embodiment, aneural network implementation extracts features of each rendered scene,potentially combining details from multiple frames, to construct ahigh-quality final image.

In deep learning implementations, parallel matrix multiplication workmay be scheduled for execution on the tensor cores 1540. The training ofneural networks, in particular, requires a significant number matrix dotproduct operations. In order to process an inner-product formulation ofan N×N×N matrix multiply, the tensor cores 1540 may include at least Ndot-product processing elements. Before the matrix multiply begins, oneentire matrix is loaded into tile registers and at least one column of asecond matrix is loaded each cycle for N cycles. Each cycle, there are Ndot products that are processed.

Matrix elements may be stored at different precisions depending on theparticular implementation, including 16-bit words, 8-bit bytes (e.g.,INT8) and 4-bit half-bytes (e.g., INT4). Different precision modes maybe specified for the tensor cores 1540 to ensure that the most efficientprecision is used for different workloads (e.g., such as inferencingworkloads which can tolerate quantization to bytes and half-bytes).

In one embodiment, the ray tracing cores 1550 accelerate ray tracingoperations for both real-time ray tracing and non-real-time ray tracingimplementations. In particular, the ray tracing cores 1550 include raytraversal/intersection circuitry for performing ray traversal usingbounding volume hierarchies (BVHs) and identifying intersections betweenrays and primitives enclosed within the BVH volumes. The ray tracingcores 1550 may also include circuitry for performing depth testing andculling (e.g., using a Z buffer or similar arrangement). In oneimplementation, the ray tracing cores 1550 perform traversal andintersection operations in concert with the image denoising techniquesdescribed herein, at least a portion of which may be executed on thetensor cores 1540. For example, in one embodiment, the tensor cores 1540implement a deep learning neural network to perform denoising of framesgenerated by the ray tracing cores 1550. However, the CPU(s) 1599,graphics cores 1530, and/or ray tracing cores 1550 may also implementall or a portion of the denoising and/or deep learning algorithms.

In addition, as described above, a distributed approach to denoising maybe employed in which the GPU 1505 is in a computing device coupled toother computing devices over a network or high speed interconnect. Inthis embodiment, the interconnected computing devices share neuralnetwork learning/training data to improve the speed with which theoverall system learns to perform denoising for different types of imageframes and/or different graphics applications.

In one embodiment, the ray tracing cores 1550 process all BVH traversaland ray-primitive intersections, saving the graphics cores 1530 frombeing overloaded with thousands of instructions per ray. In oneembodiment, each ray tracing core 1550 includes a first set ofspecialized circuitry for performing bounding box tests (e.g., fortraversal operations) and a second set of specialized circuitry forperforming the ray-triangle intersection tests (e.g., intersecting rayswhich have been traversed). Thus, in one embodiment, the multi-coregroup 1500A can simply launch a ray probe, and the ray tracing cores1550 independently perform ray traversal and intersection and return hitdata (e.g., a hit, no hit, multiple hits, etc) to the thread context.The other cores 1530, 1540 are freed to perform other graphics orcompute work while the ray tracing cores 1550 perform the traversal andintersection operations.

In one embodiment, each ray tracing core 1550 includes a traversal unitto perform BVH testing operations and an intersection unit whichperforms ray-primitive intersection tests. The intersection unitgenerates a “hit”, “no hit”, or “multiple hit” response, which itprovides to the appropriate thread. During the traversal andintersection operations, the execution resources of the other cores(e.g., graphics cores 1530 and tensor cores 1540) are freed to performother forms of graphics work.

In one particular embodiment described below, a hybrid rasterization/raytracing approach is used in which work is distributed between thegraphics cores 1530 and ray tracing cores 1550.

In one embodiment, the ray tracing cores 1550 (and/or other cores 1530,1540) include hardware support for a ray tracing instruction set such asMicrosoft's DirectX Ray Tracing (DXR) which includes a DispatchRayscommand, as well as ray-generation, closest-hit, any-hit, and missshaders, which enable the assignment of unique sets of shaders andtextures for each object. Another ray tracing platform which may besupported by the ray tracing cores 1550, graphics cores 1530 and tensorcores 1540 is Vulkan 1.1.85. Note, however, that the underlyingprinciples of the invention are not limited to any particular raytracing ISA.

In general, the various cores 1550, 1540, 1530 may support a ray tracinginstruction set that includes instructions/functions for ray generation,closest hit, any hit, ray-primitive intersection, per-primitive andhierarchical bounding box construction, miss, visit, and exceptions.More specifically, one embodiment includes ray tracing instructions toperform the following functions:

Ray Generation—Ray generation instructions may be executed for eachpixel, sample, or other user-defined work assignment.

Closest Hit—A closest hit instruction may be executed to locate theclosest intersection point of a ray with primitives within a scene.

Any Hit—An any hit instruction identifies multiple intersections betweena ray and primitives within a scene, potentially to identify a newclosest intersection point.

Intersection—An intersection instruction performs a ray-primitiveintersection test and outputs a result.

Per-primitive Bounding box Construction—This instruction builds abounding box around a given primitive or group of primitives (e.g., whenbuilding a new BVH or other acceleration data structure).

Miss—Indicates that a ray misses all geometry within a scene, orspecified region of a scene.

Visit—Indicates the children volumes a ray will traverse.

Exceptions—Includes various types of exception handlers (e.g., invokedfor various error conditions).

Lossy and Lossless Packet Compression in a Distributed Ray TracingSystem

In one embodiment, ray tracing operations are distributed across aplurality of compute nodes coupled together over a network. FIG. 16, forexample, illustrates a ray tracing cluster 1600 comprising a pluralityof ray tracing nodes 1610-1613 perform ray tracing operations inparallel, potentially combining the results on one of the nodes. In theillustrated architecture, the ray tracing nodes 1610-1613 arecommunicatively coupled to a client-side ray tracing application 1630via a gateway.

One of the difficulties with a distributed architecture is the largeamount of packetized data that must be transmitted between each of theray tracing nodes 1610-1613. In one embodiment, both losslesscompression techniques and lossy compression techniques are used toreduce the data transmitted between the ray tracing nodes 1610-1613.

To implement lossless compression, rather than sending packets filledwith the results of certain types of operations, data or commands aresent which allow the receiving node to reconstruct the results. Forexample, stochastically sampled area lights and ambient occlusion (AO)operations do not necessarily need directions. Consequently, in oneembodiment, a transmitting node will simply send a random seed which isthen used by the receiving node to perform random sampling. For example,if a scene is distributed across nodes 1610-1612, to sample light 1 atpoints p1-p3, only the light ID and origins need to be sent to nodes1610-1612. Each of the nodes may then stochastically sample the lightindependently. In one embodiment, the random seed is generated by thereceiving node. Similarly, for primary ray hit points, ambient occlusion(AO) and soft shadow sampling can be computed on nodes 1610-1612 withoutwaiting for the original points for successive frames. Additionally, ifit is known that a set of rays will go to the same point light source,instructions may be sent identifying the light source to the receivingnode which will apply it to the set of rays. As another example, ifthere are N ambient occlusion rays transmitted a single point, a commandmay be sent to generate N samples from this point.

Various additional techniques may be applied for lossy compression. Forexample, in one embodiment, a quantization factor may be employed toquantize all coordinate values associated with the BVH, primitives, andrays. In addition, 32-bit floating point values used for data such asBVH nodes and primitives may be converted into 8-bit integer values. Inone particular implementation, the bounds of ray packets are stored inin full precision but individual ray points P1-P3 are transmitted asindexed offsets to the bounds. Similarly, a plurality of localcoordinate systems may be generated which use 8-bit integer values aslocal coordinates. The location of the origin of each of these localcoordinate systems may be encoded using the full precision (e.g., 32-bitfloating point) values, effectively connecting the global and localcoordinate systems.

The following is an example of lossless compression employed in oneembodiment of the invention. A n example of a Ray data format usedinternally in a ray tracing program is as follows:

struct Ray {  uint32 pixId;  uint32 materialID;  uint32 instanceID; uint64 primitiveID;  uint32 geometryID;  uint32 lightID;  floatorigin[3];  float direction[3];  float t0;  float t;  float time;  floatnormal[3]; //used for geometry intersections  float u;  float v;  floatwavelength;  float phase; //Interferometry  float refractedOffset;//Schlieren-esque  float amplitude;  float weight;  };

Instead of sending the raw data for each and every node generated, thisdata can be compressed by grouping values and by creating implicit raysusing applicable metadata where possible.

Bundling and Grouping Ray Data

One embodiment uses flags for common data or masks with modifiers.

struct RayPacket {  uint32 size;  uint32 flags;  list<Ray> rays; } Forexample: RayPacket.rays = ray_1 to ray_256

Origins are all Shared

All ray data is packed, except only a single origin is stored across allrays. RayPacket.flags is set for RAYPACKET_COMMON_ORIGIN. When RayPacketis unpacked when received, origins are filled in from the single originvalue.

Origins are Shared Only Among Some Rays

All ray data is packed, except for rays that share origins. For eachgroup of unique shared origins, an operator is packed on that identifiesthe operation (shared origins), stores the origin, and masks which raysshare the information. Such an operation can be done on any sharedvalues among nodes such as material IDs, primitive IDs, origin,direction, normals, etc.

struct RayOperation {  uint8 operationID;  void* value;  uint64 mask; }

Sending Implicit Rays

Often times, ray data can be derived on the receiving end with minimalmeta information used to generate it. A very common example isgenerating multiple secondary rays to stochastically sample an area.Instead of the sender generating a secondary ray, sending it, and thereceiver operating on it, the sender can send a command that a ray needsto be generated with any dependent information, and the ray is generatedon the receiving end. In the case where the ray needs to be firstgenerated by the sender to determine which receiver to send it to, theray is generated and the random seed can be sent to regenerate the exactsame ray.

For example, to sample a hit point with 64 shadow rays sampling an arealight source, all 64 rays intersect with regions from the same computeN4. A RayPacket with common origin and normal is created. More datacould be sent if one wished the receiver to shade the resulting pixelcontribution, but for this example let us assume we wish to only returnwhether a ray hits another nodes data. A RayOperation is created for agenerate shadow ray operation, and is assigned the value of the lightIDto be sampled and the random number seed. When N4 receives the raypacket, it generates the fully filled Ray data by filling in the sharedorigin data to all rays and setting the direction based on the lightIDstochastically sampled with the random number seed to generate the samerays that the original sender generated. When the results are returned,only binary results for every ray need be returned, which can be handedby a mask over the rays.

Sending the original 64 rays in this example would have used 104Bytes*64 rays=6656 Bytes. If the returning rays were sent in their rawform as well, than this is also doubled to 13312 Bytes. Using losslesscompression with only sending the common ray origin, normal, and raygeneration operation with seed and ID, only 29 Bytes are sent with 8Bytes returned for the was intersected mask. This results in a datacompression rate that needs to be sent over the network of ˜360:1. Thisdoes not include overhead to process the message itself, which wouldneed to be identified in some way, but that is left up to theimplementation. Other operations may be done for recomputing ray originand directions from the pixelD for primary rays, recalculating pixelIDsbased on the ranges in the raypacket, and many other possibleimplementations for recomputation of values. Similar operations can beused for any single or group of rays sent, including shadows,reflections, refraction, ambient occlusion, intersections, volumeintersections, shading, bounced reflections in path tracing, etc.

FIG. 17 illustrates additional details for two ray tracing nodes1710-1711 which perform compression and decompression of ray tracingpackets. In particular, in one embodiment, when a first ray tracingengine 1730 is ready to transmit data to a second ray tracing engine1731, ray compression circuitry 1720 performs lossy and/or losslesscompression of the ray tracing data as described herein (e.g.,converting 32-bit values to 8-bit values, substituting raw data forinstructions to reconstruct the data, etc). The compressed ray packets1701 are transmitted from network interface 1725 to network interface1726 over a local network (e.g., a 10 Gb/s, 100 Gb/s Ethernet network).Ray decompression circuitry then decompresses the ray packets whenappropriate. For example, it may execute commands to reconstruct the raytracing data (e.g., using a random seed to perform random sampling forlighting operations). Ray tracing engine 1731 then uses the receiveddata to perform ray tracing operations.

In the reverse direction, ray compression circuitry 1741 compresses raydata, network interface 1726 transmits the compressed ray data over thenetwork (e.g., using the techniques described herein), ray decompressioncircuitry 1740 decompresses the ray data when necessary and ray tracingengine 1730 uses the data in ray tracing operations. Althoughillustrated as a separate unit in FIG. 17, ray decompression circuitry1740-1741 may be integrated within ray tracing engines 1730-1731,respectively. For example, to the extent the compressed ray datacomprises commands to reconstruct the ray data, these commands may beexecuted by each respective ray tracing engine 1730-1731.

As illustrated in FIG. 18, ray compression circuitry 1720 may includelossy compression circuitry 1801 for performing the lossy compressiontechniques described herein (e.g., converting 32-bit floating pointcoordinates to 8-bit integer coordinates) and lossless compressioncircuitry 1803 for performing the lossless compression techniques (e.g.,transmitting commands and data to allow ray recompression circuitry 1821to reconstruct the data). Ray decompression circuitry 1721 includeslossy decompression circuitry 1802 and lossless decompression circuitry1804 for performing lossless decompression.

A method in accordance with one embodiment is illustrated in FIG. 39.The method may be implemented on the ray tracing architectures describedherein but is not limited to any particular architecture.

At 3900, ray data is received which will be transmitted from a first raytracing node to a second ray tracing node. At 3901, lossy compressioncircuitry performs lossy compression on first ray tracing data and, at3902, lossless compression circuitry performs lossless compression onsecond ray tracing data. At 3903, the compressed ray racing data istransmitted to a second ray tracing node. At 3904, lossy/losslessdecompression circuitry performs lossy/lossless decompression of the raytracing data and, at 3905, the second ray tracing node performs raytracing operations sing the decompressed data.

Graphics Processor with Hardware Accelerated Hybrid Ray Tracing

One embodiment of the invention includes a hybrid rendering pipelinewhich performs rasterization on graphics cores 1530 and ray tracingoperations on the ray tracing cores 1550, graphics cores 1530, and/orCPU 1599 cores. For example, rasterization and depth testing may beperformed on the graphics cores 1530 in place of the primary ray castingstage. The ray tracing cores 1550 may then generate secondary rays forray reflections, refractions, and shadows. In addition, certainembodiments may select certain regions of a scene in which the raytracing cores 1550 will perform ray tracing operations (e.g., based onmaterial property thresholds such as high reflectivity levels) whileother regions of the scene will be rendered with rasterization on thegraphics cores 1530. In one embodiment, this hybrid implementation isused for real-time ray tracing applications—where latency is a criticalissue.

One embodiment of the ray traversal architecture described belowperforms programmable shading and control of ray traversal usingexisting single instruction multiple data (SIMD) and/or singleinstruction multiple thread (SIMT) graphics processors whileaccelerating critical functions, such as BVH traversal and/orintersections, using dedicated hardware. In this embodiment, SIMDoccupancy for incoherent paths is improved by regrouping spawned shadersat specific points during traversal and before shading. This is achievedusing dedicated hardware that sorts shaders dynamically, on-chip.Recursion is managed by splitting a function into continuations thatexecute upon returning and regrouping continuations before execution forimproved SIMD occupancy.

Programmable control of ray traversal/intersection is achieved bydecomposing traversal functionality into an inner traversal that can beimplemented as fixed function hardware and an outer traversal thatexecutes on GPU processors and enables programmable control through userdefined traversal shaders. The cost of transferring the traversalcontext between hardware and software is reduced by conservativelytruncating the inner traversal state during the transition between innerand outer traversal.

Programmable control of ray tracing can be expressed through thedifferent shader types listed in Table A below. There can be multipleshaders for each type. For example each material can have a differenthit shader.

TABLE A Shader Type Functionality Primary Launching primary rays HitBidirectional reflectance distribution function (BRDF) sampling,launching secondary rays Any Hit Computing transmittance for alphatextured geometry Miss Computing radiance from a light sourceIntersection Intersecting custom shapes Traversal Instance selection andtransformation Callable A general-purpose function

In one embodiment, recursive ray tracing is initiated by an API functionthat commands the graphics processor to launch a set of primary shadersor intersection circuitry which can spawn ray-scene intersections forprimary rays. This in turn spawns other shaders such as traversal, hitshaders, or miss shaders. A shader that spawns a child shader can alsoreceive a return value from that child shader. Callable shaders aregeneral-purpose functions that can be directly spawned by another shaderand can also return values to the calling shader.

FIG. 19 illustrates an embodiment of a graphics processing architecturewhich includes shader execution circuitry 1900 and fixed functioncircuitry 1910. The general purpose execution hardware subsystemincludes a plurality of single instruction multiple data (SIMD) and/orsingle instructions multiple threads (SIMT) cores/execution units (EUs)1901 (i.e., each core may comprise a plurality of execution units), oneor more samplers 1902, and a Level 1 (L1) cache 1903 or other form oflocal memory. The fixed function hardware subsystem 1910 includesmessage unit 1904, a scheduler 1907, ray-BVH traversal/intersectioncircuitry 1905, sorting circuitry 1908, and a local L1 cache 1906.

In operation, primary dispatcher 1909 dispatches a set of primary raysto the scheduler 1907, which schedules work to shaders executed on theSIMD/SIMT cores/EUs 1901. The SIMD cores/EUs 1901 may be ray tracingcores 1550 and/or graphics cores 1530 described above. Execution of theprimary shaders spawns additional work to be performed (e.g., to beexecuted by one or more child shaders and/or fixed function hardware).The message unit 1904 distributes work spawned by the SIMD cores/EUs1901 to the scheduler 1907, accessing the free stack pool as needed, thesorting circuitry 1908, or the ray-BVH intersection circuitry 1905. Ifthe additional work is sent to the scheduler 1907, it is scheduled forprocessing on the SIMD/SIMT cores/EUs 1901. Prior to scheduling, thesorting circuitry 1908 may sort the rays into groups or bins asdescribed herein (e.g., grouping rays with similar characteristics). Theray-BVH intersection circuitry 1905 performs intersection testing ofrays using BVH volumes. For example, the ray-BVH intersection circuitry1905 may compare ray coordinates with each level of the BVH to identifyvolumes which are intersected by the ray.

Shaders can be referenced using a shader record, a user-allocatedstructure that includes a pointer to the entry function, vendor-specificmetadata, and global arguments to the shader executed by the SIMDcores/EUs 1901. Each executing instance of a shader is associated with acall stack which may be used to store arguments passed between a parentshader and child shader. Call stacks may also store references to thecontinuation functions that are executed when a call returns.

FIG. 20 illustrates an example set of assigned stacks 2001 whichincludes a primary shader stack, a hit shader stack, a traversal shaderstack, a continuation function stack, and a ray-BVH intersection stack(which, as described, may be executed by fixed function hardware 1910).New shader invocations may implement new stacks from a free stack pool2002. The call stacks may be cached in a local L1 cache 1903, 1906 toreduce the latency of accesses.

In one embodiment, there are a finite number of call stacks, each with afixed maximum size “Sstack” allocated in a contiguous region of memory.Therefore the base address of a stack can be directly computed from astack index (SID) as base address=SID*Sstack. In one embodiment, stackIDs are allocated and deallocated by the scheduler 1907 when schedulingwork to the SIMD cores/EUs 1901.

In one embodiment, the primary dispatcher 1909 comprises a graphicsprocessor command processor which dispatches primary shaders in responseto a dispatch command from the host (e.g., a CPU). The scheduler 1907receives these dispatch requests and launches a primary shader on a SIMDprocessor thread if it can allocate a stack ID for each SIMD lane. StackIDs are allocated from the free stack pool 2002 that is initialized atthe beginning of the dispatch command.

An executing shader can spawn a child shader by sending a spawn messageto the messaging unit 1904. This command includes the stack IDsassociated with the shader and also includes a pointer to the childshader record for each active SIMD lane. A parent shader can only issuethis message once for an active lane. In one embodiment, after sendingspawn messages for all relevant lanes, the parent shader terminates.

A shader executed on the SIMD cores/EUs 1901 can also spawnfixed-function tasks such as ray-BVH intersections using a spawn messagewith a shader record pointer reserved for the fixed-function hardware.As mentioned, the messaging unit 1904 sends spawned ray-BVH intersectionwork to the fixed-function ray-BVH intersection circuitry 1905 andcallable shaders directly to the sorting circuitry 1908. In oneembodiment, the sorting circuitry groups the shaders by shader recordpointer to derive a SIMD batch with similar characteristics.Accordingly, stack IDs from different parent shaders can be grouped bythe sorting circuitry 1908 in the same batch. The sorting circuitry 1908sends grouped batches to the scheduler 1907 which accesses the shaderrecord from graphics memory 2511 or the last level cache (LLC) 1920 andlaunches the shader on a processor thread.

In one embodiment, continuations are treated as callable shaders and mayalso be referenced through shader records. When a child shader isspawned and returns values to the parent shader, a pointer to thecontinuation shader record is pushed on the call stack 2001. When achild shader returns, the continuation shader record is popped from thecall stack 2001 and a continuation shader is spawned. Spawnedcontinuations go through the sorting unit similar to callable shadersand get launched on a processor thread.

As illustrated in FIG. 21, one embodiment of the sorting circuitry 1908groups spawned tasks by shader record pointers 2101A, 2101B, 2101 n tocreate SIMD batches for shading. The stack IDs or context IDs in asorted batch can be grouped from different dispatches and differentinput SIMD lanes. In one embodiment, grouping circuitry 2110 performsthe sorting using a content addressable memory (CAM) structure 2101comprising a plurality of entries with each entry identified with a tag2101. As mentioned, in one embodiment, the tag 2101 is a correspondingshader record pointer 2101A, 2101B, 2101 n. In one embodiment, the CAMstructure 2101 stores a limited number of tags (e.g. 32, 64, 128, etc)each associated with an incomplete SIMD batch corresponding to a shaderrecord pointer.

For an incoming spawn command, each SIMD lane has a corresponding stackID (shown as 16 context IDs 0-15 in each CAM entry) and a shader recordpointer 2101A-B, . . . n (acting as a tag value). In one embodiment, thegrouping circuitry 2110 compares the shader record pointer for each laneagainst the tags 2101 in the CAM structure 2101 to find a matchingbatch. If a matching batch is found, the stack ID/context ID is added tothe batch. Otherwise a new entry with a new shader record pointer tag iscreated, possibly evicting an older entry with an incomplete batch.

An executing shader can deallocate the call stack when it is empty bysending a deallocate message to the message unit. The deallocate messageis relayed to the scheduler which returns stack IDs/context IDs foractive SIMD lanes to the free pool.

One embodiment of the invention implements a hybrid approach for raytraversal operations, using a combination of fixed-function raytraversal and software ray traversal. Consequently, it provides theflexibility of software traversal while maintaining the efficiency offixed-function traversal. FIG. 22 shows an acceleration structure whichmay be used for hybrid traversal, which is a two-level tree with asingle top level BVH 2200 and several bottom level BVHs 2201 and 2202.Graphical elements are shown to the right to indicate inner traversalpaths 2203, outer traversal paths 2204, traversal nodes 2205, leaf nodeswith triangles 2206, and leaf nodes with custom primitives 2207.

The leaf nodes with triangles 2206 in the top level BVH 2200 canreference triangles, intersection shader records for custom primitivesor traversal shader records. The leaf nodes with triangles 2206 of thebottom level BVHs 2201-2202 can only reference triangles andintersection shader records for custom primitives. The type of referenceis encoded within the leaf node 2206. Inner traversal 2203 refers totraversal within each BVH 2200-2202. Inner traversal operations comprisecomputation of ray-BVH intersections and traversal across the BVHstructures 2200-2202 is known as outer traversal. Inner traversaloperations can be implemented efficiently in fixed function hardwarewhile outer traversal operations can be performed with acceptableperformance with programmable shaders. Consequently, one embodiment ofthe invention performs inner traversal operations using fixed-functioncircuitry 1910 and performs outer traversal operations using the shaderexecution circuitry 1900 including SIMD cores/EUs 1901 for executingprogrammable shaders.

In one embodiment, when a ray intersects a traversal node during aninner traversal, a traversal shader is spawned. The sorting circuitry1908 groups these shaders by shader record pointers 2101A-B, n to createa SIMD batch which is launched by the scheduler 1907 for SIMD executionon the graphics SIMD cores/EUs 1901. Traversal shaders can modifytraversal in several ways, enabling a wide range of applications. Forexample, the traversal shader can select a BVH at a coarser level ofdetail (LOD) or transform the ray to enable rigid body transformations.The traversal shader then spawns inner traversal for the selected BVH.

Inner traversal computes ray-BVH intersections by traversing the BVH andcomputing ray-box and ray-triangle intersections. Inner traversal isspawned in the same manner as shaders by sending a message to themessaging circuitry 1904 which relays the corresponding spawn message tothe ray-BVH intersection circuitry 1905 which computes ray-BVHintersections.

In one embodiment, the stack for inner traversal is stored locally inthe fixed-function circuitry 1910 (e.g., within the L1 cache 1906). Whena ray intersects a leaf node corresponding to a traversal shader or anintersection shader, inner traversal is terminated and the inner stackis truncated. The truncated stack along with a pointer to the ray andBVH is written to memory at a location specified by the calling shaderand then the corresponding traversal shader or intersection shader isspawned. If the ray intersects any triangles during inner traversal, thecorresponding hit information is provided as input arguments to theseshaders as shown in the below code. These spawned shaders are grouped bythe sorting circuitry 1908 to create SIMD batches for execution.

struct HitInfo {  float barycentrics[2];  float tmax;  boolinnerTravComplete;  uint primID;  uint geomID;  ShaderRecord*leafShaderRecord; }

Truncating the inner traversal stack reduces the cost of spilling it tomemory. One embodiment of the invention uses the approach described inRestart Trail for Stackless BVH Traversal, High Performance Graphics(2010), pp. 107-111, to truncate the stack to a small number of entriesat the top of the stack, a 42-bit restart trail and a 6-bit depth value.The restart trail indicates branches that have already been taken insidethe BVH and the depth value indicates the depth of traversalcorresponding to the last stack entry. This is sufficient information toresume inner traversal at a later time.

Inner traversal is complete when the inner stack is empty and there nomore BVH nodes to test. In this case an outer stack handler is spawnedthat pops the top of the outer stack and resumes traversal if the outerstack is not empty.

In one embodiment, outer traversal executes the main traversal statemachine and is implemented in program code executed by the shaderexecution circuitry 1900. It spawns an inner traversal query under thefollowing conditions: (1) when a new ray is spawned by a hit shader or aprimary shader; (2) when a traversal shader selects a BVH for traversal;and (3) when an outer stack handler resumes inner traversal for a BVH.

As illustrated in FIG. 23, before inner traversal is spawned, space isallocated on the call stack 2305 for the fixed-function circuitry 1910to store the truncated inner stack 2310. Offsets 2303-2304 to the top ofthe call stack and the inner stack are maintained in the traversal state2300 which is also stored in memory 2511. The traversal state 2300 alsoincludes the ray in world space 2301 and object space 2302 as well ashit information for the closest intersecting primitive.

The traversal shader, intersection shader and outer stack handler areall spawned by the ray-BVH intersection circuitry 1905. The traversalshader allocates on the call stack 2305 before initiating a new innertraversal for the second level BVH. The outer stack handler is a shaderthat is responsible for updating the hit information and resuming anypending inner traversal tasks. The outer stack handler is alsoresponsible for spawning hit or miss shaders when traversal is complete.Traversal is complete when there are no pending inner traversal queriesto spawn. When traversal is complete and an intersection is found, a hitshader is spawned; otherwise a miss shader is spawned.

While the hybrid traversal scheme described above uses a two-level BVHhierarchy, the embodiments of the invention described herein may use anarbitrary number of BVH levels with a corresponding change in the outertraversal implementation.

In addition, while fixed function circuitry 1910 is described forperforming ray-BVH intersections in the above embodiments, other systemcomponents may also be implemented in fixed function circuitry. Forexample, the outer stack handler described above may be an internal (notuser visible) shader that could potentially be implemented in the fixedfunction BVH traversal/intersection circuitry 1905. This implementationmay be used to reduce the number of dispatched shader stages and roundtrips between the fixed function intersection hardware 1905 and theprocessor.

The embodiments of the invention described here enable programmableshading and ray traversal control using user-defined functions that canexecute with greater SIMD efficiency on existing and future GPUprocessors. Programmable control of ray traversal enables severalimportant features such as procedural instancing, stochasticlevel-of-detail selection, custom primitive intersection and lazy BVHupdates.

Apparatus and Method for Quantized, Convergent, Direction-Based RaySorting

In hardware ray tracing with a SIMD architecture, one of the fundamentalproblems is to keep all the SIMD lanes effectively utilized. Forexample, each lane may concurrently operate on a separate ray and therays may be completely independent of each other. In order to bedispatched together, rays need to share common properties such as shaderprogram code and texture resources.

Additionally, it is desirable for the rays to share a common directionand intersect the same object in the same general area. This improvescache utilization because these rays will most likely use texture datathat is also spaced closely together.

The embodiments of the invention provide a power-efficient hardwaresolution to quickly determine the approximate incoming direction of aray from the point of view of the intersected object, based on its BVHbounding box. This approximation may then be used to group dispatchedrays by incoming direction.

In particular, one embodiment groups the rays based on both estimatedincoming direction and shader record ID, a user-allocated structure thatincludes a pointer to the entry function, vendor-specific metadata, andglobal arguments to the shader executed by the SIMD cores/EUs. Forexample, this embodiment groups rays that are converging on the sameintersection point. To do so, rough intersection coordinates aredetermined with the bounding box of the target object and appended tothe shader record ID to create a compound sort key. Rays that roughlyintersect the bounding box in the same location have improved chances ofbeing co-located in the object's texture space.

Additionally, the resulting secondary rays such as reflection rays,shadow rays, etc., have an improved chance of also sharing the samegeneral direction. Therefore, they may be grouped together using thesame techniques during the secondary ray dispatch. Rays intersectingdifferent instances of the same object may also be grouped.

In one embodiment illustrated in FIG. 24 a primary ray generation shader2405 executed on one or more execution units (EUs) generates sets ofprimary rays. Ray traversal circuitry/logic 2420 traverses the raysthrough a constructed bounding volume hierarchy (BVH) to identifyvolumes through which the rays pass. Intersection circuitry 2430performs intersection tests to identify objects within the volumes whichare intersected by the rays.

One embodiment of the intersection circuitry 2430 includes ray directionevaluation circuitry/logic 2435 to process an estimated incomingdirection 2436 of each of the rays using the techniques described below.In one embodiment, the ray direction evaluator 2435 generates a raydirection sort key 2438 based on the estimated ray direction 2436.

Ray sort circuitry/logic 2440 sorts the rays based on the estimated raydirection 2436 and/or ray direction sort key 2438 in combination withthe shader record ID 2437. In one embodiment, the rays are sorted intogroups within a plurality of sort FIFO queues 2400-2403. A raydispatcher 2430 then dispatches the groups of rays from the sort FIFOs2400-2403 to the EUs 2415 for further processing, traversal andintersection operations.

As mentioned, one embodiment of the ray direction evaluator 2435determines the approximate ray direction 2436 from an efficientray/bounding box test. It then constructs a direction sort key 2438based on the approximate ray direction which uses a small number of bitsto encode the ray's direction. The sort circuitry/logic 2440 uses thedirection sort key in combination with a shader record ID sort key(e.g., a concatenation of the shader record ID and additionalconfigurable fields) to group the ray traffic in the different sortFIFOs 2400-2403.

In one embodiment, the ray direction evaluator 2435 generates aquantized ray direction using the bounding box around the object that isbased on the BVH leaf node's bounding box. Because this BVH data isalready present, obtaining the BVH leaf node requires no additionaleffort to obtain. In addition, a ray/leaf node box test is performed aspart of normal ray tracing operations. One embodiment of the raydirection evaluator 2435 enhances the ray/box intersection test toextract the intersected face, and low-resolution intersectioncoordinates with that face.

In one embodiment, uniquely identifying the intersected node in the sortkey is not required. This allows rays intersecting different instancesof the same object to be grouped. Having a match on the shader record IDguards against grouping completely unrelated rays intersecting unrelatedobjects. This is particularly beneficial for scenes which include manyrepeated structures.

FIG. 25 illustrates an example volume intersected by rays 2501-2505 withsix walls A1-A2, B1-B2, and C1-C2. In one embodiment, while checking forbounding box intersection, the ray direction evaluator 2435 detectswhich of the six walls A1-A2, B1-B2, and C1-C2 were intersected. In oneembodiment, the ray direction evaluator 2435 assigns opposite sides ofthe volume identical encodings because rays generally intersect theobject from one general side of the scene. This way there are only threeunique side encodings: A, B, and C, which may be encoded in a 2-bitnumber. It is very unlikely for rays to come from exactly opposite sidesof the object. If this happens, then the ray direction evaluator 2435can gracefully revert to using the shader record ID 2437 for grouping.

In one embodiment, 2-dimensional ray intersection coordinates aregenerated to identify the intersection point on the intersected wall.These coordinates are than reduced in precision such that they can fitwithin a sort key of a specified size. By way of example, and notlimitation, intersection calculations can be performed in reducedprecision floating point formats or fixed point formats (e.g., Int4,Int8, Bfloat16, etc). In one particular implementation, 3-bit precisionis used to encode each of the 2D coordinates. Thus, a 2-bit sideencoding, and 3-bit values for each of U and V can be packed within an8-bit field of the sort key.

This low coordinate resolution has numerous benefits. First, given thatthe sort key size is not often increased, an 8-bit value is a reasonablecompromise. Rays are only roughly grouped by their intersection pointswithout starving the dispatcher 2430 by waiting for a ray that is veryclosely packed with the ones already waiting. The circuitry required tocreate the ray/bounding box intersection points described herein cantake advantage of existing traversal/intersection circuitry andoperations. The embodiments of the invention will not require thesignificant number of additional gates typically associated with precisefloating-point calculations.

The creation of a quantized direction sort key will be described withrespect to FIG. 25. Rays 2501 and 2502 should be dispatched togetherbecause they will intersect the object contained within this boundingbox in a similar location. Rays 2503 and 2504 are not co-located becausethey intersect different walls of the bounding box (i.e., as indicatedby different side IDs). Ray 2505 hits the same wall as 2501 and 2502 butat a different location. Consequently, Ray 2505 will have the same sideID but different U/V coordinates.

FIG. 26 illustrates one embodiment of a sort key 2600 comprising ashader record key 2601 and an intersection key 2602. The intersectionkey of this embodiment comprise the 8-bit values described above—i.e., 6bits for the U and V coordinates (i.e., bits 39:34) and a 2-bit side ID(i.e., bits 33:32). The bits of the 8-bit intersection key 2602 whichchange most frequently (i.e., the U[0] and V[0] values) are encoded inthe most significant bit positions of the sort key 2600. In a way, thebits are sorted by their entropy. The reason for this particular swizzleis that the sort accuracy can be easily adjusted by changing only thenumber of sort key bits to match. In one implementation, the lowestaccuracy (1) is achieved by matching only the least significant 32 bits,which encode the shader record ID (i.e., bits 31:0). The highestaccuracy (5) is achieved by matching all 40 bits.

In one embodiment, the sorting circuitry/logic 2440 uses the adjustablesort key accuracy and fills the sort FIFOs 2403 in accordance with thefollowing set of rules, described with respect to the flowchart in FIG.27.

At 2701, when a new ray is received for sorting, the precision P isinitially set to the highest value (e.g., 40 bits in one embodiment). Ifa match is found, determined at 2702, then the ray is submitted to thecorresponding sort FIFO at 2706. If a match is not found at 2702 and ifall sort FIFOs are allocated, determined at 2703, then precision isreduced by a specified increment at 2705. An attempt to locate a matchat the lower precision is made at 2702 and, if one is found, the ray isadded to the sort FIFO at 2706. If not, then the precision may continueto be lowered at 2705 until a match is found at 2702.

If sort FIFOs are available at 2703, after determining no match at 2702,then a new sort FIFO is formed at 2704 at the current precision P (e.g.,the highest precision). As mentioned, the new sort FIFO may have thesame shader record key 2601 as an existing sort FIFO (but with adifferent intersection key). The current ray is added to the new sortFIFO and the next ray is selected at 2707.

Thus, in this embodiment, when all sort FIFOs 2400-2403 are allocatedand there are no exact 40-bit sort key matches, the precision is reduceduntil a match is found or until the precision has reached a minimumvalue (i.e., the 32-bit shader record ID 2601). When some sort FIFOs areavailable and there is no exact 40-bit sort key match, a new sort FIFOis formed for this unmatched sort key. The shader record ID may thus beduplicated across multiple FIFOs. In one embodiment, during forcedeviction of partially occupied sort FIFOs, rays may be combined acrossdifferent sort FIFOs as long as the shader record IDs 2601 match.

This approach improves the memory efficiency of the hardware raytracing, which improves performance as well as reduces powerconsumption. Ray tracing is said to replace traditional rasterizationtechniques in the future. We need to be highly competitive onperformance in order to win the high-end graphics market segment.

In embodiments, the term “engine” or “module” or “logic” may refer to,be part of, or include an application specific integrated circuit(ASIC), an electronic circuit, a processor (shared, dedicated, orgroup), and/or memory (shared, dedicated, or group) that execute one ormore software or firmware programs, a combinational logic circuit,and/or other suitable components that provide the describedfunctionality. In embodiments, an engine, module, or logic may beimplemented in firmware, hardware, software, or any combination offirmware, hardware, and software.

EXAMPLES

The following are example implementations of different embodiments ofthe invention.

Example 1. An apparatus comprising: a ray generator to generate aplurality of rays; ray direction evaluation circuitry/logic to generateapproximate ray direction data for each of the plurality of rays; andray sorting circuitry/logic to sort the rays into a plurality of rayqueues based, at least in part, on the approximate ray direction data.

Example 2. The apparatus of example 1 wherein the approximate raydirection data comprises a quantized direction value associated witheach ray of the plurality of rays.

Example 3. The apparatus of example 2 wherein the quantized directionvalue for each ray comprises first data indicating a side of a volumeintersected by the ray and second data comprising quantized intersectioncoordinates of an intersection between the ray and the side of thevolume.

Example 4. The apparatus of example 2 wherein the ray sortingcircuitry/logic is to group one or more of the plurality of rays intothe plurality of ray queues based on a combination of the quantizeddirection value and a shader record key associated with the ray.

Example 5. The apparatus of example 4 wherein the ray sortingcircuitry/logic is to first attempt to match a ray with a ray queueusing both the quantized ray direction value and the shader record keyand to attempt to match the ray with a ray queue using only the shaderrecord key only when a match is not found.

Example 6. The apparatus of example 5 wherein when a match is not foundusing the both the quantized ray direction value and the shader recordkey, the ray sorting circuitry/logic is to attempt to allocate a new rayqueue containing the ray.

Example 7. The apparatus of example 6 wherein the sortingcircuitry/logic is to attempt to match the ray with a ray queue usingonly the shader record key only after determining that the new ray queuecannot be allocated.

Example 8. The apparatus of example 1 further comprising: a raydispatcher to dispatch the plurality of rays in groups defined by theray queues in which the rays are stored.

Example 9. The apparatus of example 1 further comprising: ray traversalcircuitry to traverse one or more of the plurality of rays through abounding volume hierarchy; and ray intersection circuitry to determineintersections between one or more of the plurality of rays and one ormore objects in a scene.

Example 10. A method comprising: generating a plurality of rays;determining approximate ray direction data for each of the plurality ofrays; and sorting the rays into a plurality of ray queues based, atleast in part, on the approximate ray direction data.

Example 11. The method of example 10 wherein the approximate raydirection data comprises a quantized direction value associated witheach ray of the plurality of rays.

Example 12. The method of example 11 wherein the quantized directionvalue for each ray comprises first data indicating a side of a volumeintersected by the ray and second data comprising quantized intersectioncoordinates of an intersection between the ray and the side of thevolume.

Example 13. The method of example 11 wherein sorting further comprises:grouping the plurality of rays into the plurality of ray queues based ona combination of the quantized direction value and a shader record keyassociated with the ray.

Example 14. The method of example 13 further comprising: initiallyattempting to match a ray with a ray queue using both the quantized raydirection value and the shader record key; and attempting to match theray with a ray queue using only the shader record key only when a matchis not found.

Example 15. The method of example 14 further comprising: attempting toallocate a new ray queue containing the ray when a match is not foundusing the both the quantized ray direction value and the shader recordkey.

Example 16. The method of example 15 wherein attempting to match the raywith a ray queue using only the shader record key is performed onlyafter determining that the new ray queue cannot be allocated.

Example 17. The method of example 10 further comprising: dispatching theplurality of rays in groups defined by the ray queues in which the raysare stored.

Example 18. The method of example 10 further comprising: traversing oneor more of the plurality of rays through a bounding volume hierarchy;and determining intersections between one or more of the plurality ofrays and one or more objects in a scene.

Example 19. A machine-readable medium having program code stored thereonwhich, when executed by a machine, causes the machine to perform theoperations of: generating a plurality of rays; determining approximateray direction data for each of the plurality of rays; and sorting therays into a plurality of ray queues based, at least in part, on theapproximate ray direction data.

Example 20. The machine-readable medium of example 19 wherein theapproximate ray direction data comprises a quantized direction valueassociated with each ray of the plurality of rays.

Example 21. The machine-readable medium of example 20 wherein thequantized direction value for each ray comprises first data indicating aside of a volume intersected by the ray and second data comprisingquantized intersection coordinates of an intersection between the rayand the side of the volume.

Example 22. The machine-readable medium of example 20 wherein sortingfurther comprises: grouping the plurality of rays into the plurality ofray queues based on a combination of the quantized direction value and ashader record key associated with the ray.

Example 23. The machine-readable medium of example 22 further comprisingprogram code to cause the machine to perform the operations of:initially attempting to match a ray with a ray queue using both thequantized ray direction value and the shader record key; and attemptingto match the ray with a ray queue using only the shader record key onlywhen a match is not found.

Example 24. The machine-readable medium of example 23 furthercomprising: attempting to allocate a new ray queue containing the raywhen a match is not found using the both the quantized ray directionvalue and the shader record key.

Example 25. The machine-readable medium of example 24 wherein attemptingto match the ray with a ray queue using only the shader record key isperformed only after determining that the new ray queue cannot beallocated.

Example 26. The machine-readable medium of example 19 further comprisingprogram code to cause the machine to perform the operations of:dispatching the plurality of rays in groups defined by the ray queues inwhich the rays are stored.

Example 27. The machine-readable medium of example 19 further comprisingprogram code to cause the machine to perform the operations of:traversing one or more of the plurality of rays through a boundingvolume hierarchy; and determining intersections between one or more ofthe plurality of rays and one or more objects in a scene.

Embodiments of the invention may include various steps, which have beendescribed above. The steps may be embodied in machine-executableinstructions which may be used to cause a general-purpose orspecial-purpose processor to perform the steps. Alternatively, thesesteps may be performed by specific hardware components that containhardwired logic for performing the steps, or by any combination ofprogrammed computer components and custom hardware components.

As described herein, instructions may refer to specific configurationsof hardware such as application specific integrated circuits (ASICs)configured to perform certain operations or having a predeterminedfunctionality or software instructions stored in memory embodied in anon-transitory computer readable medium. Thus, the techniques shown inthe figures can be implemented using code and data stored and executedon one or more electronic devices (e.g., an end station, a networkelement, etc.). Such electronic devices store and communicate(internally and/or with other electronic devices over a network) codeand data using computer machine-readable media, such as non-transitorycomputer machine-readable storage media (e.g., magnetic disks; opticaldisks; random access memory; read only memory; flash memory devices;phase-change memory) and transitory computer machine-readablecommunication media (e.g., electrical, optical, acoustical or other formof propagated signals—such as carrier waves, infrared signals, digitalsignals, etc.).

In addition, such electronic devices typically include a set of one ormore processors coupled to one or more other components, such as one ormore storage devices (non-transitory machine-readable storage media),user input/output devices (e.g., a keyboard, a touchscreen, and/or adisplay), and network connections. The coupling of the set of processorsand other components is typically through one or more busses and bridges(also termed as bus controllers). The storage device and signalscarrying the network traffic respectively represent one or moremachine-readable storage media and machine-readable communication media.Thus, the storage device of a given electronic device typically storescode and/or data for execution on the set of one or more processors ofthat electronic device. Of course, one or more parts of an embodiment ofthe invention may be implemented using different combinations ofsoftware, firmware, and/or hardware. Throughout this detaileddescription, for the purposes of explanation, numerous specific detailswere set forth in order to provide a thorough understanding of thepresent invention. It will be apparent, however, to one skilled in theart that the invention may be practiced without some of these specificdetails. In certain instances, well known structures and functions werenot described in elaborate detail in order to avoid obscuring thesubject matter of the present invention. Accordingly, the scope andspirit of the invention should be judged in terms of the claims whichfollow.

1. (canceled)
 2. An apparatus comprising: execution circuitry coupled tonon-transitory machine-readable storage medium that stores instructions,which when executed by the execution circuitry, are capable ofperforming: generating a plurality of rays; generating ray directiondata to estimate directions for the plurality of rays; and sorting therays into a plurality of ray groups based on the ray direction data. 3.The apparatus of claim 2, wherein generation of the ray direction datacomprises performing a ray and bounding box intersection test.
 4. Theapparatus of claim 3, wherein a direction sort key is constructed basedon the ray and bounding box intersection test.
 5. The apparatus of claim4, wherein sorting the rays is based on the direction sort key.
 6. Theapparatus of claim 4, wherein the direction sort key comprisesintersection coordinates determined based on the ray and bounding boxintersection test.
 7. The apparatus of claim 6, wherein precision of theintersection coordinates is reduced to fit within a specified size ofthe direction sort key.
 8. The apparatus of claim 3, wherein secondaryrays based on the ray and bounding box intersection test are sorted intoa same group.
 9. The apparatus of claim 2, wherein sorting the rays isfurther based on a shader record identifier.
 10. The apparatus of claim2, wherein rays within a ray group of the plurality of ray groups aredeemed to converge on a same intersection point.
 11. The apparatus ofclaim 2, wherein rays within a ray group of the plurality of ray groupsare stored in a queue.
 12. A method comprising: generating a pluralityof rays; generating ray direction data to estimate directions for theplurality of rays; and sorting the rays into a plurality of ray groupsbased on the ray direction data.
 13. The method of claim 12, whereingeneration of the ray direction data comprises performing a ray andbounding box intersection test.
 14. The method of claim 13, wherein adirection sort key is constructed based on the ray and bounding boxintersection test.
 15. The method of claim 13, wherein secondary raysbased on the ray and bounding box intersection test are sorted into asame group.
 16. The method of claim 12, wherein sorting the rays isfurther based on a shader record identifier.
 17. The method of claim 12,wherein rays within a ray group of the plurality of ray groups arestored in a queue.
 18. A non-transitory machine-readable medium havingprogram code stored thereon which, when executed by a machine, arecapable of causing the machine to perform: generating a plurality ofrays; generating ray direction data to estimate directions for theplurality of rays; and sorting the rays into a plurality of ray groupsbased on the ray direction data.
 19. The non-transitory machine-readablemedium of claim 18, wherein generation of the ray direction datacomprises performing a ray and bounding box intersection test.
 20. Thenon-transitory machine-readable medium of claim 18, wherein sorting therays is further based on a shader record identifier.
 21. Thenon-transitory machine-readable medium of claim 18, wherein rays withina ray group of the plurality of ray groups are stored in a queue.